Methods for independent memory bank maintenance and memory devices and systems employing the same

Patent metadata

Field	Value
Publication number	US-2024257858-A1
Application number	US-202418435696-A
Country	US
Kind code	A1
Filing date	Feb 7, 2024
Priority date	Dec 29, 2017
Publication date	Aug 1, 2024
Grant date	—

Abstract

Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

First claim

1 . (canceled)

2 . A method, comprising:
storing a plurality of counters, each counter of the plurality of counters corresponding to a respective memory bank of a plurality of memory banks of a memory device; transmitting a refresh command directed to a first memory bank of the plurality of memory banks; and updating a counter of the plurality of counters in response to the refresh command, the counter corresponding to the first memory bank of the plurality of memory banks.

3 . The method of claim 2 , further comprising:
resetting the counter of the plurality of counters based at least in part on the counter exceeding a threshold.

4 . The method of claim 2 , further comprising:
transmitting a memory bank address associated with the refresh command, wherein the memory bank address identifies the first memory bank.

5 . The method of claim 2 , further comprising:
refreshing the first memory bank of the plurality of memory banks based at least in part receiving the refresh command, wherein updating the counter is further based at least in part on refreshing the first memory bank.

6 . The method of claim 2 , further comprising:
transmitting a second refresh command directed to a second memory bank of the plurality of memory banks; and updating a second counter of the plurality of counters in response to the second refresh command, the second counter corresponding to the second memory bank of the plurality of memory banks.

7 . The method of claim 6 , further comprising:
transmitting a third refresh command directed to the first memory bank of the plurality of memory banks; and updating the counter of the plurality of counters in response to the third refresh command, wherein the third refresh command is transmitted before the second refresh command.

8 . The method of claim 6 , further comprising:
refreshing the second memory bank of the plurality of memory banks based at least in part receiving the second refresh command, wherein updating the second counter is further based at least in part on refreshing the second memory bank.

9 . The method of claim 2 , wherein memory cells of the memory device comprise dynamic random access memory (DRAM) cells, ferroelectric random access memory (FeRAM) cells, magnetic random access memory (MRAM) cells, phase change memory (PCM) cells, or a combination thereof.

10 . A method, comprising:
receiving a refresh command directed to a first memory bank of a plurality of memory banks of a memory system; refreshing a first row of memory cells of the first memory bank based at least in part on a value of a first refresh counter of a plurality of refresh counters, wherein an address of the first row of memory cells is provided by the first refresh counter, and wherein a respective value of each refresh counter of the plurality of refresh counters corresponds to a respective row of memory cells of a respective memory bank of the plurality of memory banks; and incrementing the value of the first refresh counter based at least in part on refreshing the first row of memory cells.

11 . The method of claim 10 , further comprising:
receiving a second refresh command directed to a second memory bank of the plurality of memory banks; refreshing a second row of memory cells of the second memory bank based at least in part on a value of a second refresh counter of the plurality of refresh counters, wherein an address of the second row of memory cells is provided by the second refresh counter; and incrementing the value of the second refresh counter based at least in part on refreshing the second row of memory cells.

12 . The method of claim 11 , further comprising:
receiving a third refresh command directed to the first memory bank of the plurality of memory banks; refreshing a third row of memory cells of the first memory bank based at least in part on a value of the first refresh counter of the plurality of refresh counters, wherein an address of the third row of memory cells is provided by the first refresh counter; and incrementing the value of the first refresh counter based at least in part on refreshing the third row of memory cells, wherein the third refresh command is received before the second refresh command.

13 . The method of claim 10 , wherein the value of the first refresh counter comprises a row address of the first row of memory cells.

14 . The method of claim 13 , wherein incrementing the value of the first refresh counter comprises replacing the row address of the first row of memory cells with a second row address of a second row of memory cells of the first memory bank, the second row address consecutive with the row address.

15 . The method of claim 10 , wherein memory cells of the memory system comprise dynamic random access memory (DRAM) cells, ferroelectric random access memory (FeRAM) cells, magnetic random access memory (MRAM) cells, phase change memory (PCM) cells, or a combination thereof.

16 . A memory system, comprising:
one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
store a plurality of counters, each counter of the plurality of counters corresponding to a respective memory bank of a plurality of memory banks of a memory device of the one or more memory devices;
transmit a refresh command directed to a first memory bank of the plurality of memory banks; and
update a counter of the plurality of counters in response to the refresh command, the counter corresponding to the first memory bank of the plurality of memory banks.

17 . The memory system of claim 16 , wherein the processing circuitry is further configured to cause the memory system to:
reset the counter of the plurality of counters based at least in part on the counter exceeding a threshold.

18 . The memory system of claim 16 , wherein the processing circuitry is further configured to cause the memory system to:
transmit a memory bank address associated with the refresh command, wherein the memory bank address identifies the first memory bank.

19 . The memory system of claim 16 , wherein the processing circuitry is further configured to cause the memory system to:
refresh the first memory bank of the plurality of memory banks based at least in part receiving the refresh command, wherein updating the counter is further based at least in part on refreshing the first memory bank.

20 . The memory system of claim 16 , wherein the processing circuitry is further configured to cause the memory system to:
transmit a second refresh command directed to a second memory bank of the plurality of memory banks; and update a second counter of the plurality of counters in response to the second refresh command, the second counter corresponding to the second memory bank of the plurality of memory banks.

21 . The memory system of claim 20 , wherein the processing circuitry is further configured to cause the memory system to:
transmit a third refresh command directed to the first memory bank of the plurality of memory banks; and update the counter of the plurality of counters in response to the third refresh command, wherein the third refresh command is transmitted before the second refresh command.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Raad George B
• Parry Jonathan S
• Rehmeyer James S
• Cowles Timothy B

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title