Apparatus and method for asynchronous ray tracing

US2024257433A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2024257433-A1
Application numberUS-202418414841-A
CountryUS
Kind codeA1
Filing dateJan 17, 2024
Priority dateMar 15, 2020
Publication dateAug 1, 2024
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.

First claim

Opening claim text (preview).

1 . (canceled) 2 . An apparatus comprising: a storage bank to store entries of a stack, the entries corresponding to one or more nodes of a bounding volume hierarchy (BVH); traversal circuitry to perform ray traversal and/or intersection operations on one or more rays using the entries of the stack; and stack circuitry to process the entries of the stack, wherein processing a first stack entry of the stack comprises reading the first stack entry for a node from the stack and updating one or more control bits of the first stack entry. 3 . The apparatus of claim 2 , wherein updating the one or more control bits of the first stack entry causes the first stack entry to be evicted from the stack. 4 . The apparatus of claim 2 , wherein processing the first stack entry comprises popping the first stack entry and pushing a set of stack entries corresponding to one or more child nodes of the node to the stack, the one or more child nodes intersect with a ray and are sorted based on intersection distance to the ray. 5 . The apparatus of claim 4 , wherein pushing the set of stack entries causes removing, from the stack to a memory, stack entries for nodes at a higher level of the BVH. 6 . The apparatus of claim 5 , wherein the set of stack entries are loaded to the stack when the nodes at the higher level of the BVH are to be processed by the traversal circuitry. 7 . The apparatus of claim 4 , wherein popping a last stack entry of the set of stack entries causes retrieval of a root node of a second BVH. 8 . The apparatus of claim 2 , wherein the first stack entry indicates whether the node is an internal node or leaf node of the BVH. 9 . The apparatus of claim 2 , wherein the stack is a first-in and first out stack. 10 . A method comprising: storing entries of a stack in a storage bank, the entries corresponding to one or more nodes of a bounding volume hierarchy (BVH); performing, by traversal circuitry, ray traversal and/or intersection operations on one or more rays using the entries of the stack; and processing the entries of the stack, wherein processing a first stack entry of the stack comprises reading the first stack entry for a node from the stack and updating one or more control bits of the first stack entry. 11 . The method of claim 10 , wherein updating the one or more control bits of the first stack entry causes the first stack entry to be evicted from the stack. 12 . The method of claim 10 , wherein processing the first stack entry comprises popping the first stack entry and pushing a set of stack entries corresponding to one or more child nodes of the node to the stack, the one or more child nodes intersect with a ray and are sorted based on intersection distance to the ray. 13 . The method of claim 12 , wherein pushing the set of stack entries causes removing, from the stack to a memory, stack entries for nodes at a higher level of the BVH. 14 . The method of claim 13 , wherein the set of stack entries are loaded to the stack when the nodes at the higher level of the BVH are to be processed by the traversal circuitry. 15 . The method of claim 13 , wherein popping a last stack entry of the set of stack entries causes retrieval of a root node of a second BVH. 16 . The method of claim 10 , wherein the first stack entry indicates whether the node is an internal node or leaf node of the BVH. 17 . The method of claim 10 , wherein the stack is a first-in and first out stack. 18 . A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform: storing entries of a stack in a storage bank, the entries corresponding to one or more nodes of a bounding volume hierarchy (BVH); performing, by traversal circuitry, ray traversal and/or intersection operations on one or more rays using the entries of the stack; and processing the entries of the stack, wherein processing a first stack entry of the stack comprises reading the first stack entry for a node from the stack and updating one or more control bits of the first stack entry. 19 . The non-transitory machine-readable medium of claim 18 , wherein updating the one or more control bits of the first stack entry causes the first stack entry to be evicted from the stack. 20 . The non-transitory machine-readable medium of claim 18 , wherein processing the first stack entry comprises popping the first stack entry and pushing a set of stack entries corresponding to one or more child nodes of the node to the stack, the one or more child nodes intersect with a ray and are sorted based on intersection distance to the ray. 21 . The non-transitory machine-readable medium of claim 18 , wherein the first stack entry indicates whether the node is an internal node or leaf node of the BVH.

Assignees

Inventors

Classifications

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Single storage device · CPC title

  • G06T15/06Primary

    Ray-tracing · CPC title

  • Improving or facilitating administration, e.g. storage management · CPC title

  • involving image processing hardware · CPC title

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What does patent US2024257433A1 cover?
Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the ro…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06T15/06. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Aug 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).