Systems and methods for use of capacitive member to prevent chip fraud

US2024256818A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2024256818-A1
Application numberUS-202418635108-A
CountryUS
Kind codeA1
Filing dateApr 15, 2024
Priority dateDec 20, 2019
Publication dateAug 1, 2024
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Example embodiments of systems and methods for preventing chip fraud are provided. A chip fraud prevention system may comprise a device including a chip, wherein the chip is at least partially encompassed in a chip pocket. One or more connections may be communicatively coupled to one or more surfaces of the chip, and a capacitance member may be coupled to a surface of the chip. The capacitance member may comprise a known capacitance value and the chip may comprise a memory containing an applet, wherein the applet is configured to measure the capacitance value of the capacitance member.

First claim

Opening claim text (preview).

1 - 62 . (canceled) 63 . A method of preventing chip fraud, the method comprising the steps of: measuring, by an applet in the memory of a chip installed in smart card, an initial capacitance value from the smart card; measuring, by the applet in the memory of the chip installed in the smart card, a subsequent capacitance value from the smart card; and comparing the initial capacitance value against the subsequent capacitance value. 64 . The method of claim 63 further comprising, issuing a fraud alert based on the comparison resulting in a difference between the initial capacitance value and the subsequent capacitance value. 65 . The method of claim 63 wherein the measuring of the subsequent capacitance value is triggered by a transaction request. 66 . The method of claim 65 further comprising, denying the transaction request based on the comparison resulting in a difference between the initial capacitance value and the subsequent capacitance value. 67 . The method of claim 63 further comprising, updating the initial capacitance value based on a determination that a change in the initial capacitance value over time is a result of normal wear-and-tear of the smart card. 68 . The method of claim 64 wherein the fraud alert is issued only when the difference between the initial capacitance value and the subsequent capacitance value exceeds a predetermined range. 69 . The method of claim 66 wherein the transaction request is denied only when the difference between the initial capacitance value and the subsequent capacitance value exceeds a predetermined range. 70 . The method of claim 63 wherein the capacitance value from the smart card is generated by a metallic feature of the smart card. 71 . The method of claim 70 wherein the metallic feature comprises a capacitance member attached to the smart card. 72 . The method of claim 71 wherein the capacitance member comprises one or more of a wire, a coil, a plate, a disc, a particle, and a flake. 73 . A chip fraud prevention system comprising: a chip installed in a smart card, the chip comprising a memory containing an applet configured to: measure an initial capacitance value from the smart card; measure a subsequent capacitance value from the smart card; and compare the initial capacitance value against the subsequent capacitance value. 74 . The system of claim 73 wherein the applet is further configured to issue a fraud alert based on the comparison resulting in a difference between the initial capacitance value and the subsequent capacitance value. 75 . The system of claim 73 wherein the measuring of the subsequent capacitance value is triggered by a transaction request. 76 . The system of claim 75 wherein the applet is further configured to deny the transaction request based on the comparison resulting in a difference between the initial capacitance value and the subsequent capacitance value. 77 . The system of claim 73 wherein the applet is further configured to update the initial capacitance value based on a determination that a change in the initial capacitance value over time is a result of normal wear-and-tear of the smart card. 78 . The system of claim 74 wherein the fraud alert is issued only when the difference between the initial capacitance value and the subsequent capacitance value exceeds a predetermined range. 79 . The system of claim 76 wherein the transaction request is denied only when the difference between the initial capacitance value and the subsequent capacitance value exceeds a predetermined range. 80 . The system of claim 73 wherein the capacitance value from the smart card is generated by a metallic feature of the smart card. 81 . The system of claim 80 wherein the metallic feature comprises a capacitance member attached to the smart card. 82 . A smart card comprising: a chip embedded in the smart card, the chip comprising a memory containing an applet configured to: measure an initial capacitance value from the smart card; measure a subsequent capacitance value from the smart card; and compare the initial capacitance value against the subsequent capacitance value.

Assignees

Inventors

Classifications

  • protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

  • by detecting tampering with the circuit · CPC title

  • by hindering electromagnetic reading or writing (jamming of communication, counter-measures H04K3/00; secret communication H04K1/00) · CPC title

  • G06K19/073Primary

    Special arrangements for circuits, e.g. for protecting identification code in memory (protection against unauthorised use of computer memory G06F12/14) · CPC title

  • Electricity · mapped topic

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What does patent US2024256818A1 cover?
Example embodiments of systems and methods for preventing chip fraud are provided. A chip fraud prevention system may comprise a device including a chip, wherein the chip is at least partially encompassed in a chip pocket. One or more connections may be communicatively coupled to one or more surfaces of the chip, and a capacitance member may be coupled to a surface of the chip. The capacitance …
Who is the assignee on this patent?
Capital One Services Llc
What technology area does this patent fall under?
Primary CPC classification G06K19/07318. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Aug 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).