Interconnect for direct memory access controllers

Patent metadata

Field	Value
Publication number	US-2024256478-A1
Application number	US-202418633984-A
Country	US
Kind code	A1
Filing date	Apr 12, 2024
Priority date	Oct 30, 2020
Publication date	Aug 1, 2024
Grant date	—

Abstract

A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

First claim

1 . An integrated circuit comprising:
a plurality of direct memory access (DMA) controllers; and an on-chip interconnect configured to implement control logic to:
convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device, wherein the read request indicates one or more secondary DMA controllers that form a proper subset of the plurality of DMA controllers; and
broadcast or multi-cast a read response by conveying respective copies of the read response from the source memory device to the primary DMA controller and the one or more secondary DMA controllers, each of the primary DMA controller and one or more secondary DMA controllers having a corresponding on-chip destination memory device included in the integrated circuit,
wherein the primary DMA controller and the one or more secondary DMA controllers are each configured to write data included in the read response to the corresponding on-chip destination memory devices for the respective primary and secondary DMA controllers.

2 . The integrated circuit of claim 1 , wherein:
a secondary DMA controller of the one or more secondary DMA controllers is configured to transmit a synchronization request to the primary DMA controller; and the on-chip interconnect is configured to implement the control logic to convey the read request from the primary DMA controller to the source memory device in response to the primary DMA controller receiving the synchronization request.

3 . The integrated circuit of claim 2 , wherein the on-chip interconnect is configured to synchronize respective memory caches of the on-chip destination memory devices by writing the data included in the read response to the on-chip destination memory devices.

4 . The integrated circuit of claim 1 , further comprising a respective plurality of processing devices communicatively coupled to the plurality of DMA controllers, wherein each processing device of the plurality of processing devices is a central processing unit (CPU), a core of a CPU, a graphics processing unit (GPU), a core of a GPU, a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC).

5 . The integrated circuit of claim 4 , wherein the read response further includes processing setting metadata that indicates a preprocessing operation that the respective processing devices are configured to apply to the data included in the read response prior to writing to data included in the read response to the destination memory devices.

6 . The integrated circuit of claim 5 , wherein the preprocessing operation is a compression operation or an encryption operation.

7 . The integrated circuit of claim 1 , wherein the read request indicates the one or more secondary DMA controllers in a response recipient indicator that includes, for each of the plurality of DMA controllers, a respective bit indicating whether that DMA controller is included in the proper subset.

8 . The integrated circuit of claim 7 , wherein the response recipient indicator is included in a header of the read request.

9 . The integrated circuit of claim 1 , wherein:
the read request further includes a sequential request indicator; and the sequential request indicator is a timestamp or a sequentially assigned identification number.

10 . The integrated circuit of claim 1 , wherein:
the read request further includes a source memory access location of a read response payload included in the read response; and the data written to the on-chip destination memory devices includes the read response payload.

11 . A method for use with an integrated circuit that includes a plurality of direct memory access (DMA) controllers and an on-chip interconnect, the method comprising implementing control logic at the on-chip interconnect at least in part by:
conveying a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device, wherein the read request indicates one or more secondary DMA controllers that form a proper subset of the plurality of DMA controllers; broadcasting or multi-cast a read response by conveying respective copies of the read response from the source memory device to the primary DMA controller and the one or more secondary DMA controllers, each of the primary DMA controller and one or more secondary DMA controllers having a corresponding on-chip destination memory device included in the integrated circuit; and at the primary DMA controller and the one or more secondary DMA controllers, writing data included in the read response to the corresponding on-chip destination memory devices for the respective primary and secondary DMA controllers.

12 . The method of claim 11 , further comprising:
at a secondary DMA controller of the one or more secondary DMA controllers, transmitting a synchronization request to the primary DMA controller; and at the on-chip interconnect, implementing the control logic to convey the read request from the primary DMA controller to the source memory device in response to the primary DMA controller receiving the synchronization request.

13 . The method of claim 12 , further comprising, at the on-chip interconnect, synchronize respective memory caches of the on-chip destination memory devices by writing the data included in the read response to the on-chip destination memory devices.

14 . The method of claim 11 , wherein:
the integrated circuit further includes a respective plurality of processing devices communicatively coupled to the plurality of DMA controllers; and the read response further includes processing setting metadata that indicates a preprocessing operation that the respective processing devices are configured to apply to the data included in the read response prior to writing to data included in the read response to the destination memory devices.

15 . The method of claim 14 , wherein the preprocessing operation is a compression operation or an encryption operation.

16 . The method of claim 11 , wherein the read request indicates the one or more secondary DMA controllers in a response recipient indicator that includes, for each of the plurality of DMA controllers, a respective bit indicating whether that DMA controller is included in the proper subset.

17 . The method of claim 16 , wherein the response recipient indicator is included in a header of the read request.

18 . The method of claim 11 , wherein:
the read request further includes a sequential request indicator; and the sequential request indicator is a timestamp or a sequentially assigned identification number.

19 . The method of claim 11 , wherein:
the read request further includes a source memory access location of a read response payload included in the read response; and the data written to the on-chip destination memory devices includes the read response payload.

20 . An integrated circuit comprising:
a plurality of direct memory access (DMA) controllers; and an on-chip interconnect configured to implement control logic to:
convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device, wherein the read request includes:
a header including a response recipient indicator specifying one or more secondary DMA controllers that form a proper subset of the plurality of DMA controllers; and
a source memory access location; and

broadcast or multi-cast a read response by conveying respective copies of the read response from the source memory device to th

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Peng Ruihua
• Tang Monica Man Kay
• Xu Xiaoling

Classifications

• G06F15/7825

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• G06F15/17375

  One dimensional, e.g. linear array, ring · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title