Dual-gate semiconductor structures for power applications

Patent metadata

Field	Value
Publication number	US-2024243197-A1
Application number	US-202318400377-A
Country	US
Kind code	A1
Filing date	Dec 29, 2023
Priority date	Jan 13, 2023
Publication date	Jul 18, 2024
Grant date	—

Abstract

This disclosure relates to a semiconductor structure and a method for fabrication of semiconductor structures, wherein the semiconductor structure is a quasi-dual-gate field-effect transistor structure having a floating ohmic contact and a field plate. The disclosed semiconductor structure comprises a substrate, a body region over the substrate having a top surface, a source ohmic contact, a drain ohmic contact, and a floating ohmic contact disposed between the source ohmic contact and the drain ohmic contact. The disclosed semiconductor structure further comprises a first dielectric layer disposed over an outermost surface of the body region, and a first gate electrode and a second gate electrode deposited in and around openings in the first dielectric layer and over opposite sides of the floating ohmic contact.

First claim

What is claimed is:

1 . A semiconductor structure comprising:
a substrate; a body region over the substrate comprising:
a source ohmic contact, a drain ohmic contact between the source ohmic contact and the drain ohmic contact; and
a channel layer having a first portion between the source ohmic contact and the floating ohmic contact and a second portion between the drain ohmic contact and the floating ohmic contact;
a first gate electrode over the first portion of the channel layer and between the source ohmic contact and the floating ohmic contact; and a second gate electrode over the second portion of the channel layer and between the drain ohmic contact and the floating ohmic contact.

2 . The semiconductor structure of claim 1 further comprising a field plate extending over the floating ohmic contact; the first gate electrode, and the second gate electrode, wherein the field plate electrically couples to at least a portion of the source ohmic contact.

3 . The semiconductor structure of claim 1 further comprising a barrier layer having a first portion over the first portion of the channel layer and between the source ohmic contact and the floating ohmic contact and a second portion over the second portion of the channel layer and between the drain ohmic contact and the floating ohmic contact.

4 . The semiconductor structure of claim 3 wherein a portion of the first gate electrode forms contact with a top surface of the first portion of the barrier layer and a portion of the second gate electrode forms contact with a top surface of the second portion of the barrier layer.

5 . The semiconductor structure of claim 4 further comprising a first passivation layer disposed over portion of top surfaces of the first and the second portion of the barrier layer, and at least partially over a top surface of the floating ohmic contact.

6 . The semiconductor structure of claim 5 further comprising a second passivation layer disposed at least partially over a top surface of the first passivation layer and top and side surfaces of the first gate electrode and the second gate electrode.

7 . The semiconductor structure of claim 6 further comprising a source electrode disposed over at least a portion of a top surface of the source ohmic contact and a drain electrode disposed over at least a portion of a top surface of the drain ohmic contact.

8 . The semiconductor structure of claim 7 further comprising a third passivation layer disposed at least partially over a surface of the second passivation layer.

9 . The semiconductor structure of claim 8 further comprising a field plate disposed over a portion of a surface of the third passivation layer above the floating ohmic contact, the first gate electrode, and the second gate electrode, wherein the field plate disposes over and electrically couples to a portion of a top surface of the source electrode.

10 . The semiconductor structure of claim 1 wherein each of the source ohmic contact, the drain ohmic contact, and the floating ohmic contact comprises one of titanium, aluminum, nickel, gold, or their composition.

11 . The semiconductor structure of claim 1 wherein a thickness of the floating ohmic contact is in the range of 50 nm to 300 nm.

12 . The semiconductor structure of claim 1 wherein a width of the floating ohmic contact is in the range of 1 um to 12 um.

13 . The semiconductor structure of claim 1 wherein a distance between a central point of the first gate electrode and a central point of the second gate electrode is in the range of 2 um to 15 um.

14 . The semiconductor structure of claim 1 wherein a distance between a central point of the first gate electrode to the floating ohmic contact is in the range of 0.2 um to 5 um.

15 . The semiconductor structure of claim 1 wherein a distance between a central point of the second gate electrode to the floating ohmic contact is in the range of 0.2 um to 5 um.

16 . The semiconductor structure of claim 1 wherein the body region further comprises a buffer layer such that the channel layer disposes over the buffer layer, the buffer layer comprising one of gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or gallium and indium nitride (InGaN) with a thickness in the range of 100 nm to 2000 nm.

17 . The semiconductor structure of claim 1 wherein the channel layer comprises gallium nitride (GaN) with a thickness in the range of 10-nm to 300 nm.

18 . The semiconductor structure of claim 1 wherein the body region further comprises a barrier layer disposed over the channel layer, wherein the barrier layer comprises various compositions of aluminum gallium nitride with a thickness in the range of 2 nm to 40 nm.

19 . The semiconductor structure of claim 1 wherein the substrate comprises one of silicon, silicon carbide (SiC), or sapphire.

20 . The semiconductor structure of claim 1 wherein the structure is a dual-gate high electron mobility transistor (HEMT).

21 . The semiconductor structure of claim 1 wherein the structure is a gallium nitride-based dual-gate high electron mobility transistor (HEMT).

22 . A mobile terminal with power amplifier circuitry having a dual-gate HEMT, the dual-gate HEMT comprising:
a substrate; a body region over the substrate comprising:
a source ohmic contact, a drain ohmic contact, and a floating ohmic contact between the source ohmic contact and the drain ohmic contact; and
a channel layer having a first portion between the source ohmic contact and the floating ohmic contact and a second portion between the drain ohmic contact and the floating ohmic contact;
a first gate electrode over the first portion of the channel layer and between the source ohmic contact and the floating ohmic contact; and a second gate electrode over the second portion of the channel layer and between the drain ohmic contact and the floating ohmic contact.

23 . A user device with power amplifier circuitry having a dual-gate HEMT, the dual-gate HEMT comprising:
a substrate; a body region over the substrate comprising:
a source ohmic contact, a drain ohmic contact, and a floating ohmic contact between the source ohmic contact and the drain ohmic contact; and
a channel layer having a first portion between the source ohmic contact and the floating ohmic contact and a second portion between the drain ohmic contact and the floating ohmic contact;
a first gate electrode over the first portion of the channel layer and between the source ohmic contact and the floating ohmic contact; and a second gate electrode over the second portion of the channel layer and between the drain ohmic contact and the floating ohmic contact.

24 . A method of fabricating a semiconductor structure, comprising:
providing a substrate; providing a body region over the substrate, wherein:
a source ohmic contact, a drain ohmic contact, and a floating ohmic contact between the source ohmic contact and the drain ohmic contact are formed; and
forming a channel layer having a first portion between the source ohmic contact and the floating ohmic contact and a second portion between the drain ohmic contact and the floating ohmic contact;
forming a first gate electrode over the first portion of the channel layer and between the source ohmic contact and the floating ohmic contact; and forming a second gate electrode over the second portion of the channel layer and between the drain oh

Assignees

• Qorvo Us Inc

Inventors

• Reese Elias
• Shahverdi Amin
• Klemmer Nikolaus

Classifications

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D64/411

  for FETs · CPC title

• H10D64/111

  Field plates · CPC title

• H10D64/01

  Manufacture or treatment · CPC title