Semiconductor device

Patent metadata

Field	Value
Publication number	US-2024243173-A1
Application number	US-202418618329-A
Country	US
Kind code	A1
Filing date	Mar 27, 2024
Priority date	Jul 26, 2018
Publication date	Jul 18, 2024
Grant date	—

Abstract

A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2≥(L1/2) is satisfied.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a base; a first field effect transistor that includes at least two laminated channel structure portions, each laminated channel structure portion including a channel portion; and a second field effect transistor that includes a channel forming layer, a gate insulation layer formed on a top surface and a side surface of the channel forming layer, and a gate electrode formed on at least a top surface of the gate insulation layer, wherein the first field effect transistor and the second field effect transistor are provided above the base, wherein each channel portion of the first field effect transistor are disposed apart from each other in a laminating direction of the at least two laminated channel structure portions, wherein an insulation material layer is formed between a surface of the base and a bottom surface of the channel forming layer constituting the second field effect transistor, and wherein assuming that a thickness of each of the channel portions is T 1-CH and that a thickness of the insulation material layer is T Ins ,

0
.
5

≤

T
⁢
1
-
CH
/
TIns

≤
1

is satisfied.

2 . The semiconductor device according to claim 1 , wherein at least one semiconductor layer is formed between the channel forming layer and the insulation material layer in the second field effect transistor.

3 . The semiconductor device according to claim 2 , wherein an interlayer insulation layer is formed between the channel forming layer and the at least one semiconductor layer.

4 . The semiconductor device according to claim 2 , wherein the at least one semiconductor layer has a conductivity type opposite to a conductivity type of the channel forming layer.

5 . The semiconductor device according to claim 1 , wherein each of the channel portions of the first field effect transistor are at least partially surrounded by a corresponding gate insulation film.

6 . The semiconductor device according to claim 1 , wherein each of the channel portions of the first field effect transistor have a nanowire structure.

7 . The semiconductor device according to claim 1 , wherein each of the channel portions of the first field effect transistor are at least partially surrounded by a corresponding gate insulation film.

8 . The semiconductor device according to claim 7 , wherein a gate electrode surrounds at least a part of each corresponding gate insulation film.

9 . A semiconductor device, comprising:
a base; a first field effect transistor that includes at least two laminated channel structure portions, each laminated channel structure portion including a channel portion that has a nanowire structure or a nanosheet structure, a gate insulation film that surrounds the channel portion, and a gate electrode that surrounds at least a part of the gate insulation film; and a second field effect transistor that includes a channel forming layer, a gate insulation layer surrounding the channel forming layer, and a gate electrode surrounding at least a part of the gate insulation layer, wherein the first field effect transistor and the second field effect transistor are provided above the base, wherein the channel portions of the first field effect transistor are disposed apart from each other in a laminating direction of the at least two laminated channel structure portions, and wherein assuming that each of a distance between the channel portions of the first field effect transistor is a distance L1 and that a distance between a surface of the base and the channel forming layer of the second field effect transistor is a distance L2,

L
⁢
2

≥

L
⁢
1

is satisfied.

10 . The semiconductor device according to claim 9 , wherein assuming that a thickness of the gate insulation layer of the second field effect transistor is a thickness T 2 ,

T
⁢
2

≥

(

L
⁢
1
/
2

)

is satisfied.

11 . The semiconductor device according to claim 10 , wherein T 2 ≥1.1×(L 1 /2) is satisfied.

12 . The semiconductor device according to claim 10 , wherein L 2 ≥T 2 is satisfied.

13 . The semiconductor device according to claim 9 ,
wherein the second field effect transistor includes an n-channel type field effect transistor and a p-channel type field effect transistor, wherein a channel forming layer of the n-channel type field effect transistor includes silicon, and wherein a channel forming layer of the p-channel type field effect transistor includes silicon or silicon-germanium.

14 . The semiconductor device according to claim 9 ,
wherein the first field effect transistor includes an n-channel type field effect transistor and a p-channel type field effect transistor, wherein a channel portion of the n-channel type field effect transistor includes silicon, and wherein a channel portion of the p-channel type field effect transistor includes silicon-germanium, germanium, or InGaAs.

15 . A semiconductor device, comprising:
a base; a first field effect transistor including at least two laminated channel structure portions, each laminated channel structure portions including a channel portion that has a nanowire structure or a nanosheet structure, a gate insulation film that surrounds the channel portion, and a gate electrode that surrounds at least a part of the gate insulation film; and a second field effect transistor including a channel forming layer, a gate insulation layer formed on a top surface and side surfaces of the channel forming layer, and a gate electrode formed on at least a top surface of the gate insulation layer; and an insulation material layer formed between the base and a bottom surface of the channel forming layer of the second field effect transistor, wherein reverse bias is applied to the base at a portion facing the bottom surface of the channel forming layer of the second field effect transistor via the insulation material layer.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Gocho Tetsuo
• Fukuzaki Yuzo
• Miyake Shinichi
• Tomida Kazuyuki

Classifications

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D30/6743

  Silicon · CPC title