Display device

Patent metadata

Field	Value
Publication number	US-2024224668-A1
Application number	US-202318535747-A
Country	US
Kind code	A1
Filing date	Dec 11, 2023
Priority date	Dec 30, 2022
Publication date	Jul 4, 2024
Grant date	—

Abstract

A display device includes a substrate having an active area including a plurality of pixels and a non-active area surrounding the active area; an inorganic insulating layer on the substrate and extending from the active area to the non-active area; a gate in panel (GIP) driving circuit in the non-active area and applying a gate signal to each of the plurality of sub pixels in the active area; a plurality of gate link lines which transmits a gate driving signal transmitted from the outside to the GIP driving circuit; a plurality of low potential voltage lines which transmits a low potential voltage to the GIP driving circuit; and at least one of first heat transfer prevention patterns disposed in an area in which the low potential voltage is applied from the plurality of low potential voltage lines to the GIP driving circuit.

First claim

What is claimed is:

1 . A display device, comprising:
a substrate having an active area including a plurality of sub pixels and a non-active area surrounding the active area; an inorganic insulating layer disposed on the substrate and extending from the active area to the non-active area; a gate in panel (GIP) driving circuit disposed in the non-active area and applying a gate signal to each of the plurality of sub pixels in the active area; a plurality of gate link lines which transmits a gate driving signal transmitted from the outside to the GIP driving circuit; a plurality of low potential voltage lines which transmits a low potential voltage to the GIP driving circuit; and at least one of first heat transfer prevention patterns disposed in an area in which the low potential voltage is applied from the plurality of low potential voltage lines to the GIP driving circuit.

2 . The display device according to claim 1 , wherein the substrate is formed of one of a transparent conducting oxide material and an oxide semiconductor material.

3 . The display device according to claim 1 , wherein the at least one of first heat transfer prevention patterns is disposed in at least one of an area between the GIP driving circuit and the plurality of low potential voltage lines and an area between the plurality of low potential voltage lines.

4 . The display device according to claim 3 , wherein the at least one of first heat transfer prevention patterns is disposed in holes of the substrate and the inorganic insulating layer disposed in the area between the GIP driving circuit and the plurality of low potential voltage lines or the area between the plurality of low potential voltage lines, and
wherein the at least one of first heat transfer prevention patterns is formed of a material having a thermal conductivity lower than the inorganic insulating layer.

5 . The display device according to claim 4 , wherein the at least one of first heat transfer prevention patterns is configured by one of polyimide, urethane, and air.

6 . The display device according to claim 1 , further comprising a second heat transfer prevention pattern disposed in an area between the plurality of gate link lines and the GIP driving circuit.

7 . The display device according to claim 6 , further comprising at least one of third heat transfer prevention patterns disposed in an area between the plurality of gate link lines.

8 . The display device according to claim 1 , further comprising:
an electrostatic discharge circuit disposed in the non-active area and configured to discharge overcurrent or static electricity generated in the plurality of gate link lines; a plurality of first connection lines disposed in the non-active area and connecting the plurality of gate link lines and the electrostatic discharge circuit; and a plurality of second connection lines disposed in the non-active area and connecting the plurality of gate link lines and the GIP driving circuit.

9 . The display device according to claim 8 , further comprising a fourth heat transfer prevention pattern disposed in at least one of an area between the electrostatic discharge circuit and the plurality of first connection lines and an area between the plurality of first connection lines.

10 . The display device according to claim 9 , further comprising a fifth heat transfer prevention pattern disposed between the electrostatic discharge circuit and the GIP driving circuit.

11 . The display device according to claim 10 , further comprising a sixth heat transfer prevention pattern disposed in at least one of an area between the GIP driving circuit and the plurality of second connection lines and an area between the plurality of second connection lines.

12 . The display device according to claim 1 , wherein the GIP driving circuit is configured by a plurality of stages,
wherein each of the plurality of stages and the plurality of low potential voltage lines are connected, and wherein the at least one of first heat transfer prevention patterns is disposed in at least one of an area between the plurality of stages and the plurality of low potential voltage lines and an area between the plurality of low potential voltage lines.

13 . The display device according to claim 1 , further comprising an overcoating layer disposed on the inorganic insulating layer,
wherein the first heat transfer prevention pattern is formed of a same material as the overcoating layer.

14 . A display device, comprising:
a substrate having an active area including a plurality of sub pixels and a non-active area surrounding the active area; an inorganic insulating layer on the substrate and extending from the active area to the non-active area; a gate in panel driving circuit in the non-active area and applying a gate signal to each of the plurality of sub pixels in the active area; a plurality of wiring lines which transmits various driving signal to the gate in panel driving circuit; and at least one of heat transfer prevention pattern is disposed in at least one of an area between the gate in panel driving circuit and the plurality of wiring lines and an area between the plurality of wiring lines.

Assignees

• Lg Display Co Ltd

Inventors

• Yohn Gyujae
• Song Jihun

Classifications

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title