Display apparatus and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2024224619-A1
Application number	US-202318506623-A
Country	US
Kind code	A1
Filing date	Nov 10, 2023
Priority date	Dec 30, 2022
Publication date	Jul 4, 2024
Grant date	—

Abstract

A display apparatus includes a substrate having a display area in which display elements are arranged, a first thin-film transistor in the display area and including a first semiconductor layer and a first gate electrode, the first semiconductor layer including an oxide semiconductor and the first gate electrode being insulated from the first semiconductor layer, and a first interlayer insulating layer between the first semiconductor layer and the first gate electrode, wherein the first interlayer insulating layer on the first semiconductor layer has a first length in a first direction, wherein the first gate electrode on the first interlayer insulating layer has a second length in the first direction, and wherein the first length is greater than the second length.

First claim

1 What is claimed is:

1 . A display apparatus comprising:
a substrate having a display area in which display elements are arranged; a first thin-film transistor in the display area and comprising a first semiconductor layer and a first gate electrode, the first semiconductor layer comprising an oxide semiconductor and the first gate electrode being insulated from the first semiconductor layer; and a first interlayer insulating layer between the first semiconductor layer and the first gate electrode, wherein the first interlayer insulating layer on the first semiconductor layer has a first length in a first direction, wherein the first gate electrode on the first interlayer insulating layer has a second length in the first direction, and wherein the first length is greater than the second length.

2 . The display apparatus of claim 1 , further comprising a first gate insulating layer covering the first gate electrode.

3 . The display apparatus of claim 2 , further comprising:
a bottom metal layer on the substrate; and a buffer layer on the bottom metal layer.

4 . The display apparatus of claim 3 , further comprising a second interlayer insulating layer directly on at least a portion of the buffer layer and defining a contact hole therein.

5 . The display apparatus of claim 4 , further comprising a first connection electrode on the second interlayer insulating layer.

6 . The display apparatus of claim 5 , wherein the first connection electrode is electrically connected to the bottom metal layer through a contact hole defined in the second interlayer insulating layer and the buffer layer.

7 . The display apparatus of claim 3 , further comprising:
a lower electrode directly on the buffer layer; and an upper electrode over the lower electrode, wherein the upper electrode and the lower electrode form a capacitor.

8 . The display apparatus of claim 7 , wherein the first gate insulating layer is between the lower electrode and the upper electrode.

9 . The display apparatus of claim 3 , further comprising a second gate electrode on the first gate insulating layer.

10 . The display apparatus of claim 9 , wherein the second gate electrode is electrically connected to the bottom metal layer through a contact hole defined in the first gate insulating layer and the buffer layer.

11 . The display apparatus of claim 7 , further comprising:
a second gate insulating layer on the first gate insulating layer; and a second connection electrode, a source electrode, and a drain electrode on the second gate insulating layer.

12 . The display apparatus of claim 11 , wherein the second connection electrode is electrically connected to the upper electrode of the capacitor through a contact hole defined in the first interlayer insulating layer, and
wherein the source electrode and the drain electrode are electrically connected to the first semiconductor layer through contact holes defined in the first interlayer insulating layer.

13 . The display apparatus of claim 11 , further comprising:
a first organic insulating layer on the second connection electrode; and a third connection electrode on the first organic insulating layer.

14 . The display apparatus of claim 13 , wherein the third connection electrode is electrically connected to the source electrode or the drain electrode through a contact hole defined in the first organic insulating layer.

15 . A method of manufacturing a display apparatus, the method comprising:
forming a first semiconductor layer on a substrate, the first semiconductor layer comprising an oxide semiconductor; positioning a material for forming an interlayer insulating layer on the first semiconductor layer; forming a first interlayer insulating layer by patterning the material for forming the interlayer insulating layer; and forming a first gate electrode on the first interlayer insulating layer, wherein the first interlayer insulating layer on the first semiconductor layer has a first length in a first direction, wherein the first gate electrode on the first interlayer insulating layer has a second length in the first direction, and wherein the first length is greater than the second length.

16 . The method of claim 15 , further comprising, before the forming of the first semiconductor layer on the substrate:
forming a bottom metal layer on the substrate; and forming a buffer layer on the bottom metal layer, wherein the first semiconductor layer comprises the oxide semiconductor.

17 . The method of claim 16 , wherein, during the forming of the first interlayer insulating layer by patterning the material for forming the interlayer insulating layer, a second interlayer insulating layer is formed by patterning the material for forming the interlayer insulating layer.

18 . The method of claim 17 , wherein, during the forming of the first gate electrode on the first interlayer insulating layer, a first connection electrode is formed on the second interlayer insulating layer, and a lower electrode is formed on the buffer layer.

19 . The method of claim 18 , wherein the first connection electrode is electrically connected to the bottom metal layer through a contact hole defined in the second interlayer insulating layer.

20 . The method of claim 18 , further comprising:
forming a first gate insulating layer on the first gate electrode, the lower electrode, and the first connection electrode; and forming an upper electrode on the first gate insulating layer, wherein the upper electrode and the lower electrode constitute a capacitor.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Myeongho
• Kim Youngoo
• Kim Jaybum
• SON Kyoungseok
• Lee Seunghun

Classifications

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title