Apparatus and method for generating debug information

Patent metadata

Field	Value
Publication number	US-2024220395-A1
Application number	US-202218554773-A
Country	US
Kind code	A1
Filing date	Feb 10, 2022
Priority date	Apr 13, 2021
Publication date	Jul 4, 2024
Grant date	—

Abstract

An apparatus and method are described for generating debug information. The apparatus has processing circuitry for executing a sequence of instructions that includes a plurality of debug information triggering instructions, and debug information generating circuitry for coupling to a debug port. On executing a given debug information triggering instruction, the processing circuitry is arranged to trigger the debug information generating circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction. The generated debug information signal is output from the debug port for reference by a debugger. The control parameter is such that the form of the debug information signal enables the debugger to determine a state of the processing circuitry when the given debug information triggering instruction was executed.

First claim

1 . An apparatus comprising:
processing circuitry to execute a sequence of instructions that includes a plurality of debug information triggering instructions; and debug information generating circuitry for coupling to a debug port; wherein: the processing circuitry is arranged, on executing a given debug information triggering instruction in the plurality of debug information triggering instructions, to trigger the debug information generating circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction, and to output the generated debug information signal from the debug port for reference by a debugger apparatus; and the control parameter is such that the form of the debug information signal enables the debugger apparatus to determine a state of the processing circuitry when the given debug information triggering instruction was executed.

2 . An apparatus as claimed in claim 1 , wherein one or more of the debug information triggering instructions in the plurality of debug information triggering instructions has a control parameter that differs to the control parameter specified by one or more other debug information triggering instructions in the plurality of debug information triggering instructions, such that the form of the debug information signal generated by the debug information generating circuitry is dependent on which debug information triggering instruction is executed.

3 . An apparatus as claimed in claim 2 , wherein the debug information generating circuitry is arranged to generate a series of debug information signals in response to a series of debug information triggering instructions in the plurality being executed, to enable the debugger apparatus to determine the state of the processing circuitry when the given debug information triggering instruction was executed based on both the form of the debug information signal generated as a result of executing the given debug information triggering instruction and the form of one or more previously generated debug information signals.

4 . An apparatus as claimed in claim 1 , wherein the state of the processing circuitry is an indication of which instructions within the sequence of instructions had been executed by the processing circuitry at the time the given debug information triggering instruction was executed.

5 . An apparatus as claimed in claim 1 , wherein the debug information generating circuitry is arranged to determine a duration of time for which the debug information signal is output from the debug port in dependence on the control parameter specified by the given debug information triggering instruction.

6 . An apparatus as claimed in claim 5 , wherein the debug information generating circuitry is arranged to control, in dependence on the control parameter, at least one of a number of pulses, a duration of individual pulses and a time gap between pulses when generating the form of the debug information signal output during the determined duration of time.

7 . An apparatus as claimed in claim 5 , wherein the determined duration of a time is one or more clock cycles, where the number of clock cycles is dependent on the control parameter.

8 . An apparatus as claimed in claim 5 , wherein a time taken by the processing circuitry to execute the given debug information triggering instruction is independent of the determined duration of time over which the debug information signal is output from the debug port.

9 . An apparatus as claimed in claim 5 , wherein:
the debug information triggering instructions are separated from each other within the sequence of instructions by an amount that ensures that at least T clock cycles pass between execution of adjacent debug information triggering instructions; and the determined duration of time is constrained to have a maximum value of W clock cycles, where W is less than T in order to ensure a separation between each debug information signal output from the debug port.

10 . An apparatus as claimed in claim 1 , wherein the processing circuitry comprises a plurality of pipeline stages and is arranged to process each debug information triggering instruction in a manner that prevents the execution of that debug information triggering instruction causing a subsequent instruction in the sequence to stall within one or more pipeline stages of the processing circuitry.

11 . An apparatus as claimed in claim 10 , wherein the plurality of pipeline stages includes a given pipeline stage where the debug information triggering instruction becomes non-speculative, and each debug information triggering instruction is executed in a single clock cycle within the given pipeline stage.

12 . An apparatus as claimed in claim 1 , wherein the control parameter is specified as an immediate value within the given debug information triggering instruction.

13 . An apparatus as claimed in claim 1 , wherein the control parameter is specified within an opcode portion of the given debug information triggering instruction.

14 . An apparatus as claimed in claim 1 , wherein the control parameter identifies one or more registers, and the debug information generating circuitry is arranged to reference current values of those one or more registers when determining the form of the debug information signal to be generated.

15 . An apparatus as claimed in claim 1 , wherein the control parameter causes the debug information generating circuitry to derive the form of the debug information signal by modifying the form of one or more previously issued debug information signals.

16 . An apparatus as claimed in claim 1 , further comprising:
an input to receive an enable signal; wherein the debug information generating circuitry is arranged to inhibit generation of the debug information signal in the absence of the enable signal being asserted.

17 . (canceled)

18 . (canceled)

19 . An apparatus as claimed in claim 1 , wherein the apparatus is arranged to receive power from an energy harvesting source, and further comprises:
a controller to save state of the apparatus to non-volatile memory, and restore state from the non-volatile memory, in dependence on an energy state of the energy harvesting source.

20 . An apparatus as claimed in claim 1 wherein the debug information generating circuitry is arranged, in response to a calibration trigger, to output a sequence known to the debugger apparatus, for use by the debugger apparatus to calibrate for noise on a communication channel between the debug port and the debugger apparatus.

21 . A method of generating debug information, comprising:
executing within processing circuitry a sequence of instructions that includes a plurality of debug information triggering instructions; coupling debug information generating circuitry to a debug port; on executing within the processing circuitry a given debug information triggering instruction in the plurality of debug information triggering instructions, triggering the debug information generating circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction; and outputting the generated debug information signal from the debug port for reference by a debugger apparatus; wherein the control parameter is such that the form of the debug information signal enables the debugger apparatus to determine a state of the processing circuitry

Assignees

• Advanced Risc Mach Ltd

Inventors

• Savanth Parameshwarappa Anand Kumar
• Gamage Sahan Sajeewa Hiniduma Udugama
• Wang Wei
• Sandberg Andreas Lars

Classifications

• G06F11/3656

  using a specific debug interface · CPC title

• G06F11/3089

  Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents (software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466) · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title