Array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-2024213270-A1
Application number	US-202418599753-A
Country	US
Kind code	A1
Filing date	Mar 8, 2024
Priority date	Jun 28, 2022
Publication date	Jun 27, 2024
Grant date	—

Abstract

An array substrate includes a substrate, an active layer, multiple metal layers and pixel circuits. A pixel circuit of the multiple pixel circuits includes a drive transistor, a first initialization transistor, and a second initialization transistor. The multiple metal layers include a first metal wire extending in a first direction and a second metal wire extending in a second direction. The first metal wire and the second metal wire are located in different layers. The first initialization transistor is connected between the first metal wire and a gate of the drive transistor and is configured to transmit a first initialization voltage on the first metal wire to the gate of the drive transistor. The second initialization transistor is connected between the second metal wire and a light-emitting element and is configured to transmit a second initialization voltage on the second metal wire to the light-emitting element.

First claim

What is claimed is:

1 . An array substrate, comprising:
a substrate; an active layer, the active layer is disposed on one side of the substrate; a plurality of metal layers, the plurality of metal layers are disposed on one side of the substrate, the plurality of metal layers and the active layer are stacked, the plurality of metal layers at least comprise a first metal wire extending in a first direction and a second metal wire extending in a second direction, the first metal wire and the second metal wire are located in different layers, the first direction and the second direction intersect and are perpendicular to thickness direction of the array substrate, respectively; and a plurality of pixel circuits, the plurality of pixel circuits are disposed in the array substrate and a pixel circuit of the plurality of pixel circuits comprises a drive transistor, a first initialization transistor, and a second initialization transistor, the first initialization transistor is connected between the first metal wire and a gate of the drive transistor and is configured to transmit a first initialization voltage on the first metal wire to the gate of the drive transistor; the second initialization transistor is connected between the second metal wire and a light-emitting element and is configured to transmit a second initialization voltage on the second metal wire to the light-emitting element.

2 . The array substrate of claim 1 , wherein the first metal wire comprises a plurality of first sub-metal wires and a plurality of second sub-metal wires, and the plurality of first sub-metal wires and the plurality of second sub-metal wires are arranged in a plurality of columns, wherein each of the plurality of first sub-metal wires is disposed in a column, and part of the plurality of second sub-metal wires are arranged in a column;
the first initialization transistor is connected between corresponding one of the plurality of first sub-metal wires and the gate of the drive transistor; and the second initialization transistor is connected to corresponding one of the plurality of second sub-metal wires.

3 . The array substrate of claim 2 , wherein the plurality of second sub-metal wires and the plurality of first sub-metal wires are connected to form a mesh; or the plurality of second sub-metal wires and the plurality of first sub-metal wires are insulated.

4 . The array substrate of claim 3 , wherein
a first terminal of the first metal wire is connected to the second metal wire, and a second terminal of the first metal wire is connected to the first initialization transistor and the second initialization transistor; the first initialization transistor and the second initialization transistor are indirectly connected to the second metal wire via the first metal wire; and the second initialization voltage is reused as the first initialization voltage.

5 . The array substrate of claim 1 , wherein the plurality of metal layers further comprise a third metal wire and a fourth metal wire, and the third metal wire and the fourth metal wire are a first scan line and a second scan line, respectively; the third metal wire and the fourth metal wire separately extend in the second direction, and an orthographic projection of the second metal wire on the substrate is located between an orthographic projection of the third metal wire on the substrate and an orthographic projection of the fourth metal wire on the substrate; and the third metal wire overlaps the active layer to form the first initialization transistor, and the fourth metal wire overlaps the active layer to form the second initialization transistor; or
the third metal wire comprises a first body portion and a first branch portion, the fourth metal wire comprises a second body portion and a second branch portion, the first body portion and the second body portion extend in the second direction, the first branch portion and the second branch portion extend in the first direction, the first branch portion overlaps the active layer to form the first initialization transistor, and the second body portion overlaps the active layer to form the second initialization transistor.

6 . The array substrate of claim 5 , wherein the fourth metal wire corresponding to a pixel circuit of the plurality of pixel circuits in an nth row is reused as the third metal wire corresponding to a pixel circuit of the plurality of pixel circuits in an (n+1)th row, wherein n is an integer greater than or equal to 1.

7 . The array substrate of claim 1 , wherein the pixel circuit of the plurality of pixel circuits further comprises a first leakage compensation transistor and a second leakage compensation transistor, a second electrode of the first leakage compensation transistor is connected to the gate of the drive transistor, a first electrode of the first leakage compensation transistor is connected to a second electrode of the second leakage compensation transistor, and a first electrode of the second leakage compensation transistor is connected to the first initialization transistor; and
the plurality of metal layers comprise a first metal layer, a second metal layer, and a third metal layer, wherein the first metal layer comprises the gate of the drive transistor, the second metal layer comprises the second metal wire, and the third metal layer comprises the first metal wire.

8 . The array substrate of claim 7 , wherein the plurality of metal layers further comprise a fifth metal wire, and the fifth metal wire is a third scan line and is not disposed in a same layer as the first metal wire and the second metal wire; and
an orthographic projection of the fifth metal wire on the substrate is located on one side of the orthographic projection of the second metal wire on the substrate and is staggered with the orthographic projection of the second metal wire, and the fifth metal wire overlaps the active layer to form the first leakage compensation transistor and the second leakage compensation transistor.

9 . The array substrate of claim 8 , wherein the pixel circuit of the plurality of pixel circuits further comprises a first storage capacitor connected between the second metal wire and the second electrode of the second leakage compensation transistor; and
the second metal wire overlaps the active layer to form the first storage capacitor.

10 . The array substrate of claim 1 , wherein the plurality of metal layers further comprise a sixth metal wire extending in the second direction and a seventh metal wire extending in the second direction, and the sixth metal wire and the seventh metal wire are a fourth scan line and a fifth scan line, respectively; and
the sixth metal wire overlaps the active layer to form a data writing transistor and a threshold compensation transistor, and the seventh metal wire overlaps the active layer to form a first light-emitting control transistor and a second light-emitting control transistor.

11 . The array substrate of claim 10 , wherein the plurality of metal layers further comprise a fifth metal wire extending in the second direction, and the fifth metal wire is a third scan line; and
an orthographic projection of the second metal wire on the substrate is located between an orthographic projection of the fifth metal wire on the substrate and an orthographic projection of the sixth metal wire on the substrate; or, an orthographic projection of the fifth metal wire on the substrate is located between an orthographic projection of the second metal wire on the substrate and an orthographic projection of the sixth metal wire on the substrate.

12 . The array substrate of claim 11 , wherein the orthographic projec

Assignees

• Yungu Gu’An Tech Co Ltd

Inventors

• Guo Enqing
• Li Junfeng
• Gai Cuili
• Xing Rubo

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/40 Primary

  characterised by multiple TFTs · CPC title

• G09G2300/0866

  by means of changes in the pixel supply voltage · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title