Nonvolatile semiconductor memory including a read operation

Patent metadata

Field	Value
Publication number	US-2024212757-A1
Application number	US-202418596753-A
Country	US
Kind code	A1
Filing date	Mar 6, 2024
Priority date	Dec 3, 2008
Publication date	Jun 27, 2024
Grant date	—

Abstract

A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

First claim

What is claimed is:

1 . A memory device comprising:
a first transistor; a second transistor; a plurality of memory cells electrically connected in series between the first transistor and the second transistor; a source line electrically connected to the first transistor; a bit line electrically connected to the second transistor; a plurality of word lines electrically connected to gates of the plurality of memory cells, respectively; a sense amplifier including: a first node, a third transistor including i) a first end electrically connected to the bit line and ii) a second end electrically connected to the first node, a fourth transistor including a first end electrically connected i) to the second end of the third transistor and ii) to the first node, a fifth transistor including a gate electrically connected to the first node, a sixth transistor including one end electrically connected to a first end of the fifth transistor, a first latch electrically connected to a second end of the fifth transistor, and a second latch electrically connected to the second end of the fifth transistor; and a controller configured to perform an operation including: a first period, a second period after the first period, a third period after the second period, a fourth period after the third period, and a fifth period after the fourth period, at least during the second to fifth periods, a first voltage being applied to one of the plurality of word lines, and a second voltage higher than the first voltage being applied to another one of the plurality of word lines, during the first period, a third voltage being applied to a gate of the fourth transistor to turn on the fourth transistor, during the second period, a fourth voltage being applied to the gate of the fourth transistor to turn off the fourth transistor, and a fifth voltage being applied to a gate of the third transistor to turn on the third transistor, during the third period, a sixth voltage being applied to a gate of the sixth transistor to turn on the sixth transistor, during the fourth period, a seventh voltage being applied to the gate of the third transistor to turn on the third transistor, and during the fifth period, an eighth voltage being applied to the gate of the sixth transistor to turn on the sixth transistor.

2 . The memory device of claim 1 , wherein the operation includes a verify read operation.

3 . The memory device of claim 1 , wherein the sense amplifier includes a capacitor electrically connected to the first node.

4 . The memory device of claim 1 , wherein, during the second period, a ninth voltage is applied to the gate of the sixth transistor to turn off the sixth transistor.

5 . The memory device of claim 4 , wherein, during the fourth period, a tenth voltage is applied to the gate of the sixth transistor to turn off the sixth transistor.

6 . The memory device of claim 5 , wherein, during the first period, an eleventh voltage is applied to the gate of the sixth transistor to turn off the sixth transistor.

7 . The memory device of claim 1 , wherein, during the second period, a voltage of the first node is changed, according to a programmed state of a memory cell of the plurality of memory cells, the memory cell electrically connected to the one of the plurality of word lines.

8 . The memory device of claim 7 , wherein, during the fourth period, the voltage of the first node is further changed, according to the programmed state of the memory cell electrically connected to the one of the plurality of word lines.

9 . The memory device of claim 8 ,
wherein the first latch is configured to store a first bit corresponding to the change in the voltage of the first node during the second period, and wherein the second latch is configured to store a second bit corresponding to the further change in the voltage of the first node during the fourth period.

10 . The memory device according to claim 1 , wherein at least during the second to fourth periods, a voltage of the bit line is maintained at a same level.

11 . A memory device comprising:
a set of memory cells electrically connected to each other in series; a sense amplifier comprising: a first node, a first transistor including i) a first end electrically connected to the first node and ii) a second end electrically connected to one end of the set of memory cells, a second transistor including a first end electrically connected to the first node, and a third transistor including a gate electrically connected to the first node; and a controller electrically connected to the sense amplifier, wherein, to read data stored by a memory cell of the set of memory cells, the controller is configured to: enable, during a first period, the second transistor to set a voltage of the first node to be a first voltage, enable, during a second period after the first period, the first transistor to electrically connect the first node to the memory cell to change the voltage of the first node, according to a programmed state of the memory cell, disable, during a third period after the second period, the first transistor to electrically disconnect the first node from the memory cell, enable, during a fourth period after the third period, the first transistor to electrically connect the first node to the memory cell to further change the voltage of the first node, according to the programmed state of the memory cell, and disable the second transistor during the second period, the third period, and the fourth period.

12 . The memory device of claim 11 , wherein the first transistor of the sense amplifier is electrically connected to the one end of the set of memory cells through a bit line of the set of memory cells.

13 . The memory device of claim 11 , wherein the sense amplifier includes a capacitor electrically connected to the first node.

14 . The memory device of claim 11 , further comprising:
a first word line electrically connected to a gate of the memory cell of the set of memory cells; and a second word line electrically connected to a gate of another memory cell of the set of memory cells, wherein the controller is further configured to: apply, during the first period, a first voltage to the first word line, and apply, during the first period, a second voltage higher than the first voltage to the second word line.

15 . The memory device of claim 11 , wherein the controller is further configured to enable, during the first period, the first transistor to electrically connect the first node to the memory cell.

16 . The memory device of claim 11 , further comprising:
a fourth transistor electrically connected to the third transistor, wherein the controller is further configured to: disable the fourth transistor during the second period, and enable the fourth transistor during the third period.

17 . The memory device of claim 16 , wherein the controller is further configured to apply a strobe signal to a gate of the fourth transistor to thereby:
disable the fourth transistor during the fourth period, enable the fourth transistor during a fifth period after the fourth period, and disable the second transistor during the fifth period.

18 . The memory device of claim 11 , wherein the sense amplifier further includes:
a first latch electrically connected to the third transistor, and a second latch electrically connected to the third transistor.

19 . The memory device of claim 18 ,
wherein the first latch is configured to st

Assignees

• Kioxia Corp

Inventors

• Iwai Makoto
• Nakamura Hiroshi

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3436

  Arrangements for verifying correct programming or erasure · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title