Shift register unit and driving method therefor, gate drive circuit, and display device

Patent metadata

Field	Value
Publication number	US-2024203316-A1
Application number	US-202117910539-A
Country	US
Kind code	A1
Filing date	Oct 25, 2021
Priority date	Apr 8, 2021
Publication date	Jun 20, 2024
Grant date	—

Abstract

The present disclosure provides a shift register unit and a driving method therefor, a gate drive circuit, and a display device, belonging to the field of display technologies. In the shift register unit, a first input circuit can control a potential of a first node under control of a first clock signal provided by a first clock terminal and control a potential of a third node under control of a potential of a second node. A second input circuit can control the potential of the second node under control of the first clock signal, an input control signal provided by an input control terminal, the potential of the third node, and the potential of the first node. An output circuit can transmit a pull-up power signal at a high potential or a pull-down power signal at a low potential to an output terminal under control of the third node. In this way, the potential of the output terminal can be reliably controlled only by flexibly setting clock signals provided by two clock terminals and the input control signal provided by the input control terminal. The control process is simple, and the control flexibility is high.

First claim

1 . A shift register unit, comprising:
a first input circuit coupled to a first clock terminal, a first node, a second node, a third node, a pull-up power supply terminal, and a pull-down power supply terminal, wherein first input circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the first node and control the pull-down power supply terminal to be conducted or non-conducted with the first node in response to a first clock signal provided by the first clock terminal; and control the pull-up power supply terminal to be conducted or non-conducted with the third node and control the pull-down power supply terminal to be conducted or non-conducted with the third node in response to a potential of the second node; a second input circuit coupled to the first node, the second node, the third node, the pull-up power supply terminal, the pull-down power supply terminal, an input control terminal, and the first clock terminal, wherein second input circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the second node and control the pull-down power supply terminal to be conducted or non-conducted with the second node in response to a potential of the first node, a potential of the third node, the first clock signal, and an input control signal provided by the input control terminal; and an output circuit coupled to the pull-up power supply terminal, the pull-down power supply terminal, the third node, a second clock terminal, and an output terminal, wherein output circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the output terminal and control the pull-down power supply terminal to be conducted or non-conducted with the output terminal in response to the potential of the third node and a second clock signal provided by the second clock terminal.

2 . The shift register unit according to claim 1 , wherein the output circuit comprises a first output sub-circuit and a second output sub-circuit; wherein
the first output sub-circuit is coupled to the second clock terminal, the third node, the pull-up power supply terminal, the pull-down power supply terminal, and a fourth node, and is configured to control the pull-up power supply terminal to be conducted or non-conducted with the fourth node and control the pull-down power supply terminal to be conducted or non-conducted with the fourth node in response to the second clock signal and the potential of the third node; and the second output sub-circuit is coupled to the fourth node, the pull-up power supply terminal, the pull-down power supply terminal, and the output terminal, and is configured to control the pull-up power supply terminal to be conducted or non-conducted with the output terminal and control the pull-down power supply terminal to be conducted or non-conducted with the output terminal in response to a potential of the fourth node.

3 . The shift register unit according to claim 2 , wherein the first output sub-circuit comprises a first output transistor, a second output transistor, and a third output transistor, the first output transistor being a complementary metal-oxide-semiconductor (CMOS) transistor; wherein
a gate of the first output transistor is coupled to the second clock terminal, one first electrode of the first output transistor and a first electrode of the second output transistor are both coupled to the pull-up power supply terminal, the other first electrode of the first output transistor is coupled to a second electrode of the third output transistor, a second electrode of the first output transistor and a second electrode of the second output transistor are both coupled to the fourth node, a gate of the second output transistor and a gate of the third output transistor are both coupled to the third node, and a first electrode of the third output transistor is coupled to the pull-down power supply terminal.

4 . The shift register unit according to claim 2 , wherein the second output sub-circuit comprises an odd number of fourth output transistors connected in series between the fourth node and the output terminal; wherein
each of the fourth output transistors is a CMOS transistor, and two first electrodes of each of the fourth output transistors are coupled to the pull-up power supply terminal and the pull-down power supply terminal, respectively.

5 . The shift register unit according to claim 4 , wherein the second output sub-circuit comprises three fourth output transistors; wherein
a gate of a first one of the fourth output transistors is coupled to the fourth node, and a second electrode of the first one of the fourth output transistors is coupled to a gate of a second one of the fourth output transistors; a second electrode of the second one of the fourth output transistors is coupled to a gate of a third one of the fourth output transistors, and a second electrode of the third one of the fourth output transistors is coupled to the output terminal.

6 . The shift register unit according to claim 4 , wherein a width-to-length ratio of at least one of the fourth output transistors is greater than width-to-length ratios of transistors in the shift register unit except the at least one of the fourth output transistors.

7 . The shift register unit according to claim 1 , wherein the second input circuit comprises a first input sub-circuit and a second input sub-circuit; wherein
the first input sub-circuit is coupled to the first node, the first clock terminal, the input control terminal, the pull-up power supply terminal, the pull-down power supply terminal, and the second node, and is configured to control the pull-up power supply terminal to be conducted or non-conducted with the second node and control the pull-down power supply terminal to be conducted or non-conducted with the second node in response to the potential of the first node, the input control signal, and the first clock signal; and the second input sub-circuit is coupled to the first clock terminal, the first node, the second node, the third node, the pull-up power supply terminal, and the pull-down power supply terminal, and is configured to control the pull-up power supply terminal to be conducted or non-conducted with the second node and control the pull-down power supply terminal to be conducted or non-conducted with the second node in response to the potential of the first node, the potential of the third node, and the first clock signal.

8 . The shift register unit according to claim 7 , wherein the first input sub-circuit comprises a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor; the first input transistor and the third input transistor being CMOS transistors; wherein
a gate of the first input transistor is coupled to the first node, two first electrodes of the first input transistor are coupled to the pull-up power supply terminal and the pull-down power supply terminal respectively, and a second electrode of the first input transistor is coupled to a gate of the second input transistor, and the gate of the second input transistor is further coupled to the first clock terminal; a first electrode of the second input transistor is coupled to the pull-down power supply terminal and a second electrode of the second input transistor is coupled to one first electrode of the third input transistor; the other first electrode of the third input transistor is coupled to a second electrode of the fourth input transistor, a gate of the third input transistor is coupled to the input control terminal, and a second electrode of the third input transistor is coupled to the second node; and a gate of the fourth input transi

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Zhu
• Yan Zhenglong
• Lu Hui
• Liu Ke
• Shi Ling
• Chen Yipeng

Classifications

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title