Data storage device and method for performing error recovery

Patent metadata

Field	Value
Publication number	US-2024202060-A1
Application number	US-202318219714-A
Country	US
Kind code	A1
Filing date	Jul 10, 2023
Priority date	Dec 15, 2022
Publication date	Jun 20, 2024
Grant date	—

Abstract

A data storage device includes an interface circuit to process reception signals received from a peer device and transmission signals to be transmitted to the peer device. The interface circuit includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device within a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal has been received from the peer device.

First claim

What is claimed is:

1 . A data storage device, comprising:
an interface circuit, configured to process reception signals received from a peer device and transmission signals to be transmitted to the peer device, wherein the interface circuit comprises a signal processing circuit configured to perform an error recovery procedure when an error has occurred in the data storage device, and when performing the error recovery procedure, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device within a predetermined period until the predetermined period expires or until another line reset signal representing an acknowledgment of the line reset signal has been received from the peer device.

2 . The data storage device of claim 1 , wherein when determining that a first signal handshake procedure has failed, the signal processing circuit performs the operation of periodic line reset, and wherein the signal processing circuit tries to trigger the first signal handshake procedure by transmitting a first predetermined request signal to the peer device for at least one time.

3 . The data storage device of claim 2 , wherein the signal processing circuit requests to reset a current transmission rate in the first signal handshake procedure.

4 . The data storage device of claim 2 , wherein in the first signal handshake procedure, the signal processing circuit requests to maintain a current transmission rate at a predetermined transmission rate that is being used by the data storage device when the error occurred.

5 . The data storage device of claim 2 , wherein the first predetermined request signal is a power mode change request signal defined by Mobile Industry Processor Interface (MIPI) alliance.

6 . The data storage device of claim 1 , wherein the signal processing circuit transmits the line reset signal to the peer device by setting voltages on a pair of differential signal transmission paths based on a specific pattern.

7 . The data storage device of claim 1 , wherein the data storage device is comprised in a data storage system, and the peer device is a host device accessing the data storage device in the data storage system.

8 . The data storage device of claim 1 , wherein when the signal processing circuit has not received any line reset signal from the peer device when the predetermined period expires, the signal processing circuit determines that error recovery has failed, and when the signal processing circuit has received said another line reset signal from the peer device before the predetermined period expires, the signal processing circuit further transmits a second predetermined request signal to trigger a second signal handshake procedure.

9 . The data storage device of claim 8 , wherein when determining that the second signal handshake procedure has failed, the signal processing circuit determines that the error recovery has failed, and when determining that the second signal handshake procedure is successful, the signal processing circuit determines that the error recovery is successful.

10 . The data storage device of claim 8 , wherein the signal processing circuit sets a current transmission rate to a lowest transmission rate to transmit the second predetermined request signal, and requests to restore the current transmission rate to a predetermined transmission rate that is being used by the data storage device when the error occurred in the second signal handshake procedure.

11 . A method for performing error recovery, applied in an error recovery procedure performed by a signal processing circuit when an error has occurred in a data storage device, comprising:
transmitting a first predetermined request signal to a peer device to try to trigger a first signal handshake procedure; performing an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device within a predetermined period when determining that the first signal handshake procedure has failed; transmitting a second predetermined request signal to the peer device to try to trigger a second signal handshake procedure when determining that the line reset signal has been received by the peer device; and determining that error recovery is successful when the second signal handshake procedure is determined successful.

12 . The method of claim 11 , further comprising:
requesting to reset a current transmission rate in the first signal handshake procedure.

13 . The method of claim 11 , further comprising:
requesting to maintain a current transmission rate at a predetermined transmission rate that is being used by the data storage device when the error occurred in the first signal handshake procedure.

14 . The method of claim 11 , wherein the line reset signal is transmitted by setting voltages on a pair of differential signal transmission paths based on a specific pattern.

15 . The method of claim 11 , wherein the signal processing circuit is comprised in an interface circuit of the data storage device.

16 . The method of claim 11 , further comprising:
determining that the error recovery has failed when the line reset signal is determined to have not been received by the peer device, wherein when the signal processing circuit has not received any line reset signal from the peer device when the predetermined period expires, the line reset signal is determined to have not been received by the peer device.

17 . The method of claim 11 , further comprising:
determining that the error recovery has failed when the second signal handshake procedure is determined to have failed.

18 . The method of claim 11 , wherein the second predetermined request signal is transmitted at a current transmission rate which is set to a lowest transmission rate, and in the second signal handshake procedure, the current transmission rate is requested to be restored to a predetermined transmission rate that is being used by the data storage device when the error occurred.

19 . The method of claim 11 , wherein the first predetermined request signal and the second predetermined request signal are both a power mode change request signal defined by Mobile Industry Processor Interface (MIPI) alliance.

Assignees

• Silicon Motion Inc

Inventors

• Shih Fu-Jen

Classifications

• G06F11/1441

  Resetting or repowering · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/1443 Primary

  Transmit or communication errors · CPC title

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title