A memory device, a memory module, a computing system, a method for erasing a memory portion of a memory device and a method for generating an erase request

Patent metadata

Field	Value
Publication number	US-2024185905-A1
Application number	US-202118547910-A
Country	US
Kind code	A1
Filing date	Mar 26, 2021
Priority date	Mar 26, 2021
Publication date	Jun 6, 2024
Grant date	—

Abstract

A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.

First claim

1 - 25 . (canceled)

26 . A memory device comprising:
an input interface configured to receive an erase request indicating a memory portion to be erased; and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.

27 . The memory device of claim 1 , further comprising an auxiliary memory configured to store information on memory cells to be erased based on the erase request.

28 . The memory device of claim 1 , wherein the auxiliary memory is configured to store an erase indication for a plurality of memory blocks based on one or more erase requests, wherein a memory block of the plurality of memory blocks is associated to a plurality of memory cells of the memory device.

29 . The memory device of claim 3 , wherein the control circuitry is configured to check whether memory cells scheduled for auto refresh during the automatic refresh cycle are indicated for erasure in the auxiliary memory.

30 . The memory device of claim 4 , wherein the control circuitry is configured to trigger erasing the information stored by the memory cells scheduled for auto refresh instead of performing the auto refresh during the automatic refresh cycle, if the memory cells scheduled for auto refresh are indicated for erasing in the auxiliary memory.

31 . The memory device of claim 3 , wherein the control circuitry is configured to trigger an automatic refresh of a batch of rows of memory cells during an automatic refresh cycle, wherein the auxiliary memory is configured to store information indicating whether the rows of the batch of rows of memory cells should be erased by adjacent bits of the auxiliary memory.

32 . The memory device of claim 3 , wherein the auxiliary memory is an SRAM.

33 . The memory device of claim 3 , wherein the auxiliary memory and the memory cells to be erased are implemented on the same memory die.

34 . The memory device of claim 3 , comprising a plurality of auxiliary memories, wherein each auxiliary memory of the plurality of auxiliary memories is assigned to an individual memory bank of the memory device.

35 . The memory device of claim 3 , wherein the auxiliary memory and a micro controller of the memory device are implemented on the same semiconductor die.

36 . The memory device of claim 3 , wherein the auxiliary memory is connected to a plurality of memory dies, wherein the auxiliary memory is connected to store information on a first set of memory cells to be erased being located on a first memory die of the plurality of memory dies and a second set of memory cells to be erased being located on a second memory die of the plurality of memory dies.

37 . The memory device of claim 1 , wherein the control circuitry is configured to trigger erasing information stored by memory cells so that the memory cells are erased while other memory cells of the memory device are refreshed during the automatic refresh cycle.

38 . The memory device of claim 1 , wherein the memory portion indicated by the erase request comprises one or more rank address blocks identified by one or more rank addresses.

39 . The memory device of claim 13 , wherein a rank address block comprises at least a part of one row of memory cells.

40 . The memory device of claim 1 , wherein the received erase request comprises information on the predefined pattern.

41 . The memory device of claim 1 , wherein the memory cells to be erased are DRAM cells.

42 . The memory device of claim 1 , wherein the memory device is a DRAM die.

43 . The memory device of claim 1 , wherein the memory device is a memory module comprising a plurality of DRAM dies.

44 . A memory device comprising:
an input interface configured to receive an erase request indicating at least a part of one row of memory cells to be erased, wherein the input interface is further configured to receive a read or write request for at least a part of a row of memory cells; and control circuitry configured to trigger a reset of at least a part of a row buffer of a memory array comprising the row of memory cells indicated by the read or write request based on a predefined pattern during a read or write cycle assigned for the received read or write request and before outputting of information stored by one or more memory cells indicated by the read or write request or before inputting information to be stored by one or more memory cells indicated by the read or write request, if an erase request was received for at least a part of the row of memory cells indicated by the read or write request.

45 . A computing system comprising:
one or more CPUs configured to run an operating system generating an operating system erase request indicating a high level memory address to be erased; and one or more memory controllers configured to determine a memory block of a DIMM based on the operating system erase request and generate a memory controller erase request indicating the memory block to be erased during an automatic refresh cycle or read/write cycle of the DIMM.

Assignees

• Intel Corp

Inventors

• Liu Shuo
• Dong Yao Zu
• Huang Qing
• Li Kevin Yufu
• Yao Yipeng
• Yu Jie

Classifications

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/20 Primary

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title