Computation apparatus, method, system, circuit, and device, and chip

Patent metadata

Field	Value
Publication number	US-2024184521-A1
Application number	US-202418440254-A
Country	US
Kind code	A1
Filing date	Feb 13, 2024
Priority date	Aug 20, 2021
Publication date	Jun 6, 2024
Grant date	—

Abstract

The computation apparatus includes a position coordinate comparison circuit and a logical operation circuit. The position coordinate comparison circuit is configured to compare position coordinates of an element value in a first vector with position coordinates of an element value in a second vector, to obtain a coordinate comparison result. The logical operation circuit is configured to compute the first element value and the second element value based on a first comparison result, to obtain a computation value; and output a computation result to a cache. The computation result is related to the computation value. In comparison with a conventional method in which a vector in a compressed format needs to be decompressed first, and then vector computation is performed on a decompressed vector, the computation apparatus can effectively improve efficiency of computing the vector in the compressed format.

First claim

What is claimed is:

1 . A computation apparatus, comprising a position coordinate comparison circuit and a logical operation circuit, wherein
the position coordinate comparison circuit is configured to compare position coordinates of an element value in a first vector with position coordinates of an element value in a second vector, to obtain a first coordinate comparison result, wherein both the first vector and the second vector are vectors in a compressed format, the first vector comprises a first element value and first position coordinates of the first element value, the second vector comprises a second element value and second position coordinates of the second element value, the first coordinate comparison result comprises a first comparison result, and the first comparison result indicates that the first position coordinates are the same as the second position coordinates; and the logical operation circuit is configured to compute the first element value and the second element value based on the first comparison result, to obtain a computation value; and output a computation result of the first vector and the second vector to a cache, wherein the computation result is related to the computation value.

2 . The computation apparatus according to claim 1 , wherein the logical operation circuit comprises an accumulator;
the position coordinate comparison circuit is further configured to receive an addition instruction, and transmit the first comparison result to the accumulator based on the addition instruction; and the accumulator is configured to add the first element value and the second element value based on the first comparison result, to obtain a sum of the first element value and the second element value, wherein the sum is the computation value, the computation result comprises a third element value and third position coordinates of the third element value, the third element value is the sum, and the third position coordinates are the same as the first position coordinates.

3 . The computation apparatus according to claim 2 , wherein
the accumulator is further configured to: when the third element value is a zero element value, output an invalid signal for the zero element value, wherein the invalid signal indicates that an element value in a computation result does not comprise the zero element value and position coordinates corresponding to the zero element value.

4 . The computation apparatus according to claim 3 , wherein the accumulator skips, based on the invalid signal, outputting the zero element value and the position coordinates corresponding to the zero element value to the cache.

5 . The computation apparatus according to claim 2 , wherein the first coordinate comparison result further comprises a second comparison result, the first vector comprises a fourth element value and fourth position coordinates of the fourth element value, and the second comparison result indicates that no position coordinates that are the same as the fourth position coordinates are found in the second vector; and
the accumulator is further configured to output the fourth element value and the fourth position coordinates to the cache based on the second comparison result, wherein the computation result comprises the fourth element value and the fourth position coordinates.

6 . The computation apparatus according to claim 1 , wherein the logical operation circuit comprises a multiplier;
the position coordinate comparison circuit is further configured to receive a multiplication instruction, and transmit the first comparison result to the multiplier based on the multiplication instruction; and the multiplier is configured to multiply the first element value by the second element value based on the first comparison result, to obtain a product of the first element value and the second element value, wherein the product is the computation value, the computation result comprises a fifth element value and fifth position coordinates of the fifth element value, the fifth element value is the product, and the fifth position coordinates are the same as the first position coordinates.

7 . The computation apparatus according to claim 1 , wherein the logical operation circuit comprises an inner product operation circuit;
the position coordinate comparison circuit is further configured to receive an inner product instruction, and transmit the first comparison result to the inner product operation circuit based on the inner product instruction; and the inner product operation circuit is configured to multiply the first element value by the second element value based on the first comparison result, to obtain a product of the first element value and the second element value, wherein the product is the computation value, and the computation result is an accumulated value of a plurality of products.

8 . The computation apparatus according to claim 1 , wherein the logical operation circuit comprises a multiplier and an accumulator, and the first coordinate comparison result further comprises a third comparison result;
the position coordinate comparison circuit is further configured to receive a multiplication-addition computation instruction, and transmit the first comparison result to the multiplier based on the multiplication-addition computation instruction; the multiplier is further configured to multiply the first element value by the second element value based on the first comparison result, to obtain a product of the first element value and the second element value, wherein the computation value comprises the product, the product is a fifth element value, and fifth position coordinates are the same as the first position coordinates; the position coordinate comparison circuit is further configured to compare sixth position coordinates with the fifth position coordinates, to obtain the third comparison result; and transmit the third comparison result to the accumulator, wherein the third comparison result indicates that the sixth position coordinates are the same as the fifth position coordinates, the sixth position coordinates are position coordinates in a third vector, and the third vector comprises a sixth element value and the sixth position coordinates corresponding to the sixth element value; and the accumulator is configured to add the sixth element value and the fifth element value based on the third comparison result, to obtain a sum of the sixth element value and the fifth element value, wherein the computation value comprises the sum of the sixth element value and the fifth element value, the computation result comprises a seventh element value and seventh position coordinates corresponding to the seventh element value, the seventh element value is the sum of the sixth element value and the fifth element value, and the seventh position coordinates are the same as the sixth position coordinates.

9 . The computation apparatus according to claim 1 , wherein
the position coordinate comparison circuit is further configured to compare position coordinates of an element value in a first matrix with position coordinates of an element value in a second matrix, to obtain a second coordinate comparison result, wherein the first matrix comprises the first vector, the second matrix comprises the second vector, both the first matrix and the second matrix are matrices in a compressed format, and the second coordinate comparison result comprises the first coordinate comparison result.

10 . The computation apparatus according to claim 9 , wherein the position coordinate comparison circuit comprises a row coordinate comparison circuit and a column coordinate comparison circuit, a dimension of the first matrix is M×

Assignees

• Huawei Tech Co Ltd

Inventors

• Lin Tengyi
• Wang Kai
• Wang Qin

Classifications

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/02 Primary

  Comparing digital values (G06F7/06, {G06F7/22,} G06F7/38 take precedence) · CPC title

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F7/523

  Multiplying only · CPC title