Time domain analog-to-digital converter and analog-to-digital converting method

Patent metadata

Field	Value
Publication number	US-2024178857-A1
Application number	US-202318335572-A
Country	US
Kind code	A1
Filing date	Jun 15, 2023
Priority date	Nov 28, 2022
Publication date	May 30, 2024
Grant date	—

Abstract

In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.

First claim

What is claimed is:

1 . An analog-to-digital converter comprising:
a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses, the plurality of positive pulses respectively input to the plurality of stages and the plurality of negative pulses respectively input to the plurality of stages; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuits configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.

2 . The analog-to-digital converter of claim 1 , wherein
each of the plurality of stages is further configured to compare the corresponding positive pulse and the corresponding negative pulse to decide the corresponding bit, and each of a plurality of second stages among the plurality of stages is configured to generate a positive pulse to be input to a next stage among the plurality of positive pulses and a negative pulse to be input to the next stage among the plurality of negative pulses, by delaying either one of the corresponding positive pulse and the corresponding negative pulse by a corresponding reference time among a plurality of references times respectively corresponding to the plurality of second stages, the plurality of second stages not including a last stage in the sequence among the plurality of stages, the next stage being a stage after the corresponding stage in the sequence, the last stage not having a next stage in the sequence.

3 . The analog-to-digital converter of claim 2 , wherein the operation of the previous stage comprises a comparison operation of a positive pulse input to the previous stage among the plurality of positive pulses and a negative pulse input to the previous stage among the plurality of negative pulses.

4 . The analog-to-digital converter of claim 3 , wherein each of the plurality of clock generating circuits is further configured to generate the corresponding clock of the corresponding stage in response to a result of the comparison operation in the previous stage.

5 . The analog-to-digital converter of claim 3 , wherein each of the plurality of clock generating circuits is further configured to reset the corresponding clock of the corresponding stage in response to a result of the comparison operation in the corresponding stage.

6 . The analog-to-digital converter of claim 3 , wherein each of the plurality of clock generating circuits is further configured to reset the corresponding clock of the corresponding stage in response to generation of a clock in a next clock generating circuit among the plurality of clock generating circuits.

7 . The analog-to-digital converter of claim 2 , wherein each of the plurality of second stages is further configured to
delay the corresponding positive pulse by the corresponding reference time when deciding the corresponding bit as a first value, or delay the corresponding negative pulse by the corresponding reference time when deciding the corresponding bit as a second value different from the first value.

8 . The analog-to-digital converter of claim 2 , wherein, the plurality of second stages include a start stage in the sequence and at least one third stage, the start stage in the sequence not having a previous stage in the sequence, the corresponding reference time of each of the at least one third stage is half of a reference time corresponding to the previous stage among the plurality of reference times.

9 . The analog-to-digital converter of claim 1 , wherein the plurality of first stages are stages not including a start stage among the plurality of stages in the sequence, the start stage in the sequence not having a previous stage in the sequence.

10 . The analog-to-digital converter of claim 9 , wherein the corresponding clock of the start stage is an input clock of the analog-to-digital converter.

11 . The analog-to-digital converter of claim 1 , further comprising a voltage-to-time converter circuit configured to convert a positive input voltage and a negative input voltage into a time domain to generate an input positive pulse and an input negative pulse to be input to a start stage among the plurality of stages in the sequence as the corresponding positive pulse and the corresponding negative pulse of the start stage, respectively, the start stage in the sequence not having a previous stage in the sequence.

12 . The analog-to-digital converter of claim 1 , further comprising:
a voltage-to-time converter circuit configured to convert a positive input voltage and a negative input voltage into a time domain to generate an input positive pulse and an input negative pulse; and a time-to-digital converter circuit configured to decide at least one bit based on the input positive pulse and the input negative pulse, and then output a residual positive pulse and a residual negative pulse to be input to a start stage among the plurality of stages in the sequence as the corresponding positive pulse and the corresponding negative pulse, respectively, the start stage in the sequence not having a previous stage in the sequence.

13 . An analog-to-digital converter comprising:
a first time comparator configured to operate in response to a first clock, and decide a first bit based on a first comparison result of comparing a first positive pulse and a first negative pulse; a first delay circuit configured to delay either one of the first positive pulse and the first negative pulse by a first reference time based on a value of the first comparison result; a clock generating circuit configured to generate a second clock in response to the first comparison result; a second time comparator configured to operate in response to the second clock, and decide a second bit based on a second comparison result of comparing a second positive pulse and a second negative pulse output from the first delay circuit; and a second delay circuit configured to delay either one of the second positive pulse and the second negative pulse by a second reference time based on a value of the second comparison result.

14 . The analog-to-digital converter of claim 13 , wherein the clock generating circuit is further configured to reset the second clock in response to the second comparison result.

15 . The analog-to-digital converter of claim 13 , wherein the first time comparator is further configured to
output a first value as the first comparison result in response to the first positive pulse being earlier than the first negative pulse, or output a second value different from the first value as the first comparison result in response to the first negative pulse being earlier than the first positive pulse, wherein the second time comparator is further configured to
output the first value as the second comparison result in response to the second positive pulse being earlier than the second negative pulse, or
output the second value different as the second comparison result in response to the second negative pulse being earlier than the second posi

Assignees

• Samsung Electronics Co Ltd
• Univ Korea Res & Bus Found

Inventors

• Hyun Jihwan
• Kim Chulwoo
• Park Sooho
• Choi Junghwan

Classifications

• H03M1/38 Primary

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/50 Primary

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title

• G04F10/105

  with conversion of the time-intervals · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title