Semiconductor device having multiple electrostatic discharge (esd) paths

Patent metadata

Field	Value
Publication number	US-2024178216-A1
Application number	US-202418435938-A
Country	US
Kind code	A1
Filing date	Feb 7, 2024
Priority date	Sep 18, 2019
Publication date	May 30, 2024
Grant date	—

Abstract

A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
first and second doped regions that are disposed in a first well and coupled to a first voltage terminal, wherein the first and second doped regions have different conductive types; a third doped region that is in a second well and coupled to an input/output (I/O) pad, wherein the first doped region and the third doped region are configured as a first current discharge path; and a fourth doped region that is disposed in a third well, wherein the first and third wells have a first conductive type and the second well has a second conductive type; and wherein the third and the fourth doped region are configured as a second current discharge path.

2 . The semiconductor device of claim 1 , further comprising:
a fifth doped region, wherein the fourth and fifth doped regions are included in a structure operating as a first diode coupled between the I/O pad and the first voltage terminal, wherein the first and second doped regions are included in a second diode, wherein the third doped region is arranged between the first and second diodes.

3 . The semiconductor device of claim 1 , further comprising:
a plurality of fifth doped regions that are in the third well and included in a structure operating as a first diode coupled between the I/O pad and the first voltage terminal, wherein the first and second doped regions are included in a second diode, wherein the plurality of fifth doped regions are further included in the current discharge path.

4 . The semiconductor device of claim 3 , wherein the first and second diodes are arranged on opposite sides of the third doped region.

5 . The semiconductor device of claim 1 , further comprising:
a fifth doped region that is disposed in the second well and coupled to a second voltage terminal providing a second supply voltage different from a first supply voltage provided by the first voltage terminal, wherein the third and fifth doped regions and the second well are configured to transmit a second ESD current flowing between the I/O pad and the second voltage terminal.

6 . A semiconductor device, comprising:
a first doped region of a first conductivity type, wherein the first doped region is coupled to an input/output (I/O) pad and is a first terminal of a first diode; and a second doped region of a second conductivity type, wherein the second doped region is coupled to a first voltage terminal and is a first terminal of a second diode; and wherein the first to second diodes are configured to transmit a first electrostatic discharge (ESD) current flowing between the first and second doped regions.

7 . The semiconductor device of claim 6 , further comprising:
a third doped region of the first conductivity type that is in a first well and coupled to a second voltage terminal, wherein the first doped region is in the first well, wherein the first doped region, the third doped region and the first well are configured to form a second ESD path between the I/O pad and the first voltage terminal.

8 . The semiconductor device of claim 7 , further comprising:
a plurality of fourth doped regions of the second conductivity type in a third well of the second conductivity type, wherein the first well is sandwiched between the second and third wells, wherein the first doped region is further arranged between the third doped region and the plurality of fourth doped regions.

9 . The semiconductor device of claim 8 , wherein the plurality of fourth doped regions are coupled to the first voltage terminal configured to have a voltage level lower than that of the second voltage terminal.

10 . The semiconductor device of claim 6 , further comprising:
a third doped region of the second conductivity type in a third well of the second conductivity type, wherein the first well is arranged between the second and third wells, wherein the third doped region is coupled to the first voltage terminal, wherein the third doped region, the third well, the first well, and the first doped region are configured to form a second ESD path between the I/O pad and the first voltage terminal.

11 . The semiconductor device of claim 10 , further comprising:
a fourth doped region of the second conductivity type that is arranged in the third well and coupled to the first voltage terminal, wherein the first doped region, the first well, the third well, and the fourth doped region are configured to form a third ESD path between the I/O pad and the first voltage terminal.

12 . The semiconductor device of claim 6 , further comprising:
a third doped region of the first conductivity type arranged in a third well adjacent to the first well, and coupled to the I/O pad; and a plurality of fourth doped regions of the second conductivity type arranged in the third well and coupled to the first voltage terminal, wherein the third doped region is sandwiched between the first doped region and the plurality of fourth doped regions.

13 . The semiconductor device of claim 12 , wherein the first doped region, the first well, the third well and the plurality of fourth doped regions are configured to form a plurality of ESD paths between the I/O pad and the first voltage terminal.

14 . A semiconductor device, comprising:
at least one first doped region and a second doped region that are in a first well, wherein the at least one first doped region is coupled to a first voltage terminal and the second doped region is coupled to an input/output (I/O) pad; and a third doped region that is in a second well, wherein the third doped region is coupled to the I/O pad, wherein the at least one first doped region and the third doped region are configured as a latchup current path.

15 . The semiconductor device of claim 14 , further comprising:
a fourth doped region of a first conductivity type configured as a first terminal of a first diode; and a fifth doped region of a second conductivity type configured as a second terminal of the first diode, wherein the fourth and fifth doped regions are coupled to the first voltage terminal.

16 . The semiconductor device of claim 15 , further comprising:
a third well of the first conductivity type surrounding the fourth and fifth doped regions in a layout view, wherein the third doped region is of the first conductivity type and configured as a first terminal of a second diode, wherein the second well is of the second conductivity type and surrounds the third doped region in the layout view, wherein the fifth and third doped regions, the third well, and the second well are configured as a first electrostatic discharge (ESD) path between the I/O pad and the first voltage terminal.

17 . The semiconductor device of claim 16 , wherein the second well and the third well are adjacent to each other.

18 . The semiconductor device of claim 16 , wherein the fifth doped region is arranged between the third and fourth doped regions.

19 . The semiconductor device of claim 14 , further comprising:
a fourth doped region that is disposed in the second well and coupled to a second voltage terminal providing a second supply voltage different from a first supply voltage provided by the first voltage terminal, wherein the third and fourth doped regions and the second well are configured to transmit a second ESD current flowing between the I/O pad and the second voltage terminal.

20 . The semiconductor device of claim 14 , wherein the at least one first doped region comprises a p

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Chu Li-Wei
• Tsai Ming-Fu
• Lee Jam-Wem
• Su Yu-Ti

Classifications

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D84/615

  Combinations of vertical BJTs and one or more of resistors or capacitors · CPC title