Memory device and operating method of the memory device

Patent metadata

Field	Value
Publication number	US-2024177780-A1
Application number	US-202318326781-A
Country	US
Kind code	A1
Filing date	May 31, 2023
Priority date	Nov 30, 2022
Publication date	May 30, 2024
Grant date	—

Abstract

There are provided a memory device and an operating method of the memory device. The memory device includes: a plurality of pages each comprising a plurality of memory cells; a peripheral circuit for, in a read operation of a selected page among the pages, applying a read voltage to a selected word line connected to the selected page, sequentially applying sub-pass voltages and target pass voltages higher than the sub-pass voltages to adjacent word lines adjacent to the selected word line, and applying the target pass voltages to the other unselected word lines; and a control circuit for controlling the peripheral circuit. Before the read voltage is applied to the selected word line, the control circuit controls the peripheral circuit to apply the sub-pass voltages to the adjacent word lines, and apply the target pass voltages to the other unselected word lines.

First claim

What is claimed is:

1 . A memory device comprising:
a plurality of pages each comprising a plurality of memory cells; a peripheral circuit configured to, in a read operation of a selected page among the plurality of pages, apply a read voltage to a selected word line connected to the selected page, sequentially apply sub-pass voltages and target pass voltages higher than the sub-pass voltages to adjacent word lines that are unselected word lines adjacent to the selected word line, and apply the target pass voltages to other unselected word lines different from the unselected word lines adjacent to the selected word line; and a control circuit configured to control the peripheral circuit, wherein, before the read voltage is applied to the selected word line, the control circuit controls the peripheral circuit to apply the sub-pass voltages to the adjacent word lines, and apply the target pass voltages to the other unselected word lines.

2 . The memory device of claim 1 , wherein the peripheral circuit includes:
a voltage generator configured to generate and output the read voltage, the sub-pass voltages, and the target pass voltages; and a page buffer group connected to the memory cells through bit lines to sense the memory cells.

3 . The memory device of claim 1 , wherein, after the target pass voltages are applied to the other unselected word lines, the control circuit controls the peripheral circuit to:
apply the read voltage to the selected word line; and apply the target pass voltages to the adjacent word lines to which the sub-pass voltages are applied.

4 . The memory device of claim 1 , wherein the adjacent word lines are one or more adjacent lines adjacent to the selected word line respectively under and above the selected word line.

5 . The memory device of claim 1 , wherein the voltage generator stepwisely increases the sub-pass voltages applied to the adjacent word lines in a stepped form.

6 . The memory device of claim 1 , wherein the voltage generator stepwisely increases the target pass voltages applied to the adjacent word lines in a stepped form.

7 . The memory device of claim 4 , wherein the voltage generator applies the sub-pass voltages having the same level to the adjacent word lines.

8 . The memory device of claim 7 , wherein the voltage generator simultaneously applies the sub-pass voltages having the same level to the adjacent word lines.

9 . The memory device of claim 4 , wherein the voltage generator applies the sub-pass voltages having different levels to the adjacent word lines.

10 . The memory device of claim 9 , wherein the voltage generator applies the sub-pass voltages respectively to the adjacent word lines, and
wherein the sub-pass voltages are lowered as the respective adjacent word lines are closer to the selected word line.

11 . The memory device of claim 9 , wherein, after the voltage generator applies a highest voltage among the sub-pass voltages to the adjacent word lines, the voltage generator applies the target pass voltages to the adjacent word lines after a certain time.

12 . The memory device of claim 11 , wherein, the voltage generator simultaneously applies the read voltage to the selected word line when the voltage generator applies the target pass voltages to the adjacent word lines.

13 . A method of operating a memory device, the method comprising:
dividing word lines into a selected word line, adjacent word lines that are unselected word lines adjacent to the selected word line, and other unselected word lines different from the unselected word lines adjacent to the selected word line; applying target pass voltages to the other unselected word line, and applying sub-pass voltages lower than the target pass voltages to the adjacent word lines; applying the target pass voltages to the adjacent word lines, after the sub-pass voltages are applied to the adjacent word lines; and applying a read voltage to the selected word line, when the target pass voltages are applied to the adjacent word lines.

14 . The method of claim 13 , wherein the sub-pass voltages are stepwisely increased in a stepped form.

15 . The method of claim 14 , wherein the target pass voltages applied to the adjacent word lines are linearly increased.

16 . The method of claim 13 , wherein the sub-pass voltages are linearly increased.

17 . The method of claim 16 , wherein the target pass voltages applied to the adjacent word lines are stepwisely increased in a stepped form.

18 . The method of claim 13 , wherein, when a plurality of adjacent word lines among the adjacent word lines are disposed under the selected word line, and a plurality of adjacent word lines among the adjacent word lines are disposed above the selected word line, the sub-pass voltages having substantially the same level are applied to the adjacent word lines.

19 . The method of claim 13 , wherein the sub-pass voltages are simultaneously applied to the adjacent word lines.

20 . The method of claim 13 , wherein, when a plurality of adjacent word lines among the adjacent word lines are disposed under the selected word line, and a plurality of adjacent word lines among the adjacent word lines are disposed above the selected word line, the sub-pass voltage having different levels are applied to the adjacent word lines.

21 . The method of claim 20 , wherein the voltage generator applies the sub-pass voltages respectively to the adjacent word lines, and
wherein the sub-pass voltages are lowered as the respective adjacent word lines are closer to the selected word line.

22 . The method of claim 20 , wherein, after the voltage generator applies a highest voltage among the sub-pass voltages to the adjacent word lines, the voltage generator applies the target pass voltages to the adjacent word lines after a certain time.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title