Print check repeater defect detection

Patent metadata

Field	Value
Publication number	US-2024177294-A1
Application number	US-202218072605-A
Country	US
Kind code	A1
Filing date	Nov 30, 2022
Priority date	Nov 30, 2022
Publication date	May 30, 2024
Grant date	—

Abstract

Systems and methods for detecting defects on a reticle are provided. One system is configured for generating different stacked difference images for multiple instances of first patterned areas in different rows on a wafer based on images generated for the first patterned areas in the different rows. The system is also configured for performing double detection based on the different stacked difference images. The system then identifies defects on the reticle based on the defects detected by the double detection. As described further herein, the systems and methods detect defects from multiple reticle rows printed on a wafer, which can reduce noise and enable detection of substantially small repeater defects. The embodiments are particularly useful for high sensitivity repeater defect detection for extreme ultraviolet (EUV) reticles and multi-die reticles (MDR).

First claim

What is claimed is:

1 . A system configured to detect defects on a reticle, comprising:
an inspection subsystem configured to generate images for a wafer, wherein a reticle is used to print patterned areas on the wafer in a lithography process, and wherein the patterned areas comprise first patterned areas corresponding to the same area on the reticle and printed in different rows on the wafer; and a computer subsystem configured for:
generating different stacked difference images for multiple instances of the first patterned areas in the different rows based on the images generated for the first patterned areas in the different rows by the inspection subsystem;
detecting defect candidates in the multiple instances of the first patterned areas on the wafer by applying a defect detection method to the different stacked difference images, wherein the defect detection method determines that a defect candidate is present at a location in each of the multiple instances of the first patterned areas only when the defect detection method detects the defect candidate at the location in the different stacked difference images; and
identifying defects on the reticle based on the detected defect candidates.

2 . The system of claim 1 , wherein the inspection subsystem is further configured to generate the images by interleaving scanning of the first patterned areas in the different rows on the wafer with scanning of a second of the patterned areas in the different rows on the wafer.

3 . The system of claim 2 , wherein the first patterned areas and the second of the patterned areas correspond to different portions of a die on the reticle.

4 . The system of claim 2 , wherein the first patterned areas and the second of the patterned areas correspond to different instances of a die on the reticle printed on the wafer.

5 . The system of claim 1 , wherein the reticle is a multi-die reticle, and wherein the first patterned areas comprise at least a portion of only a first die of the multi-die reticle printed on the wafer.

6 . The system of claim 1 , wherein generating a first of the different stacked difference images comprises generating first and second difference images and combining at least a portion of the first and second difference images to generate the first of the different stacked difference images, and wherein generating a second of the different stacked difference images comprises generating third and fourth difference images and combining at least a portion of the third and fourth difference images to generate the second of the different stacked difference images.

7 . The system of claim 6 , wherein generating the first difference images comprises separately subtracting a first computed reference from the images generated for the multiple instances of the first patterned areas in a first of the different rows on the wafer and generating the second difference images comprises separately subtracting the first computed reference from the images generated for the multiple instances of the first patterned areas in a second of the different rows on the wafer.

8 . The system of claim 7 , wherein the computer subsystem is further configured for generating the first computed reference from the images of multiple instances of a second of the patterned areas in the different rows on the wafer.

9 . The system of claim 7 , wherein generating the third difference images comprises separately subtracting a second computed reference from the images generated for the multiple instances of the first patterned areas in the first of the different rows on the wafer and generating the fourth difference images comprises separately subtracting the second computed reference from the images generated for the multiple instances of the first patterned areas in the second of the different rows on the wafer.

10 . The system of claim 9 , wherein the computer subsystem is further configured for generating the second computed reference from the images of multiple instances of a third of the patterned areas in the different rows on the wafer.

11 . The system of claim 6 , wherein generating the first difference images comprises separately subtracting a first computed reference from the images generated for the multiple instances of the first patterned areas in a first of the different rows on the wafer and generating the second difference images comprises separately subtracting a second computed reference from the images generated for the multiple instances of the first patterned areas in a second of the different rows on the wafer.

12 . The system of claim 11 , wherein the computer subsystem is further configured for generating the first computed reference from the images of multiple instances of a second of the patterned areas in the first of the different rows on the wafer and generating the second computed reference from the images of multiple instances of the second of the patterned areas in the second of the different rows on the wafer.

13 . The system of claim 11 , wherein generating the third difference images comprises separately subtracting a third computed reference from the multiple instances of the images generated for the first patterned areas in the first of the different rows on the wafer and generating the fourth difference images comprises separately subtracting a fourth computed reference from the images generated for the multiple instances of the first patterned areas in the second of the different rows on the wafer.

14 . The system of claim 13 , wherein the computer subsystem is further configured for generating the third computed reference from the images of multiple instances of a third of the patterned areas in the first of the different rows on the wafer and generating the fourth computed reference from the images of multiple instances of the third of the patterned areas in the second of the different rows on the wafer.

15 . The system of claim 6 , wherein generating the first difference images comprises separately subtracting a first computed reference from the images generated for the multiple instances of the first patterned areas in a first of the different rows on the wafer and generating the second difference images comprises separately subtracting a second computed reference from the images generated for the multiple instances of the first patterned areas in the first of the different rows on the wafer.

16 . The system of claim 15 , wherein the computer subsystem is further configured for generating the first computed reference from the images of multiple instances of a second of the patterned areas in the first of the different rows on the wafer and generating the second computed reference from the images of multiple instances of a third of the patterned areas in the first of the different rows on the wafer.

17 . The system of claim 15 , wherein generating the third difference images comprises separately subtracting a third computed reference from the images generated for the multiple instances of the first patterned areas in a second of the different rows on the wafer and generating the fourth difference images comprises separately subtracting a fourth computed reference from the images generated for the multiple instances of the first patterned areas in the second of the different rows on the wafer.

18 . The system of claim 17 , wherein the computer subsystem is further configured for generating the third computed reference from the images of multiple instances of a second of the patterned areas in the second of the different rows on the wafer

Assignees

• Kla Corp

Inventors

• Patwary Nurmohammed
• Smith James A
• Shin Heonju
• Maeng Jusang
• Wu Kenong
• Li Xiaochun
• Lee Hucheng

Classifications

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• G06T2207/20221

  Image fusion; Image merging · CPC title

• G06T2207/20224

  Image subtraction · CPC title

• G03F1/84

  Inspecting · CPC title

• G06T5/50

  using two or more images, e.g. averaging or subtraction · CPC title