Storage device for executing background operation based on power state and operating method thereof

Patent metadata

Field	Value
Publication number	US-2024176407-A1
Application number	US-202318172477-A
Country	US
Kind code	A1
Filing date	Feb 22, 2023
Priority date	Nov 25, 2022
Publication date	May 30, 2024
Grant date	—

Abstract

A storage device may enter a plurality of intermediate power states sequentially while entering from a first power state to a second power state. The storage device may check background flag information while entering each of the plurality of intermediate power states, and execute a target background operation, executable in a first intermediate power state, based on the background flag information.

First claim

What is claimed is:

1 . A storage device comprising:
a memory including a plurality of memory blocks; and a controller configured to: enter a plurality of intermediate power states sequentially while transitioning from a first power state to a second power state, check background flag information indicating background operations executable in each of the plurality of intermediate power states when entering each of the plurality of intermediate power states, and execute a target background operation, executable in a first intermediate power state, among the executable background operations based on the background flag information, after entering the first intermediate power state and before entering a second intermediate power state.

2 . The storage device according to claim 1 ,
wherein the controller is configured to decrease an operating clock and an operating voltage when entering the second intermediate power state from the first intermediate power state.

3 . The storage device according to claim 1 ,
wherein the controller is configured to execute the target background operation for less than a set threshold execution time.

4 . The storage device according to claim 1 ,
wherein the background operations include at least one of a garbage collection on the plurality of memory blocks; flushing data stored in a buffer to the memory; migrating data stored in a first type memory block, among the plurality of memory blocks, to a second type memory block having a larger storage capacity than the first type memory block; and erasing one or more of the plurality of memory blocks.

5 . The storage device according to claim 4 ,
wherein the controller is configured to determine the background flag information so that a background operation having a higher priority is executed earlier.

6 . The storage device according to claim 5 ,
wherein the controller is configured to set the priority of the garbage collection operation to be inversely proportional to the number of free memory blocks included in the memory or to be proportional to the size of invalid data stored in the memory.

7 . The storage device according to claim 5 ,
wherein the controller is configured to set the priority of the operation migrating data from the first type memory block to the second type memory block to be inversely proportional to the size of the data to be migrated from the first type memory block to the second type memory block.

8 . The storage device according to claim 5 ,
wherein the controller is configured to set the priority of the operation flushing the data stored in the buffer to the memory to be inversely proportional to the size of the data stored in the buffer.

9 . The storage device according to claim 1 ,
wherein the controller is further configured to check whether an event instructing to return to the first power state is set in the first intermediate power state.

10 . A method for operating a storage device, comprising:
entering a first intermediate power state among a plurality of intermediate power states that are entered sequentially while transitioning from a first power state to a second power state; checking background flag information indicating background operations executable among a plurality of background operations; executing a target background operation executable in the first intermediate power state based on the background flag information; and determining whether to enter a second intermediate power state.

11 . The method according to claim 10 , further comprising:
decreasing an operating clock and an operating voltage when entering the second intermediate power state from the first intermediate power state.

12 . The method according to claim 10 ,
wherein the background operations include at least one of a garbage collection on the plurality of memory blocks; flushing data stored in a buffer to the memory; migrating data stored in a first type memory block among the plurality of memory blocks to a second type memory block having a larger storage capacity than the first type memory block; and erasing one or more of the plurality of memory blocks.

13 . The method according to claim 10 ,
wherein the background flag information determines that a background operation having a higher priority among the background operations is executed earlier.

14 . The method according to claim 13 ,
wherein the priority of the garbage collection operation is set to be inversely proportional to the number of free memory blocks included in the memory or to be proportional to the size of invalid data stored in the memory.

15 . The method according to claim 13 ,
wherein the priority of the operation migrating data from the first type memory block to the second type memory block is set to be inversely proportional to the size of the data to be migrated from the first type memory block to the second type memory block.

16 . The method according to claim 13 ,
wherein the priority of the operation flushing the data stored in the buffer to the memory is set to be inversely proportional to the size of the data stored in the buffer.

17 . A controller comprising:
a memory interface capable of communicating with a memory including a plurality of memory blocks; and a control circuit configured to: enter a plurality of intermediate power states sequentially while transitioning from a normal state consuming a first power to a low power state consuming a second power, which is less than the first power, and execute, while entering each of the plurality of intermediate power states, an executable background operation from among a plurality of background operations based on background flag information indicating executable background operations.

Assignees

• Sk Hynix Inc

Inventors

• Jang In Jong

Classifications

• G11C2029/1202

  Word line control · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/0253

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title