Vertical digit lines for semiconductor devices

Patent metadata

Field	Value
Publication number	US-2024172420-A1
Application number	US-202418428581-A
Country	US
Kind code	A1
Filing date	Jan 31, 2024
Priority date	Oct 26, 2020
Publication date	May 23, 2024
Grant date	—

Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

First claim

What is claimed is:

1 . A memory device, comprising:
an array of vertically stacked memory cells, the array having horizontally oriented access devices and access lines and vertically oriented digit lines, comprising:
the horizontally oriented access devices having first source/drain regions and second source/drain regions separated by channel regions, and gates opposing the channel regions formed fully around every surface of the channel regions as gate all around (GAA) structures on a gate dielectric material,
wherein the array of vertically stacked memory cells is electrically coupled in one of an open digit line architecture or a folded digit line architecture.

2 . The memory device of claim 1 , comprising the horizontally oriented access lines separated from the channel region by the gate dielectric material.

3 . The memory device of claim 1 , comprising horizontally oriented storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices.

4 . The memory device of claim 1 , comprising the vertically oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices.

5 . The memory device of claim 1 , wherein the channel regions are deposited horizontally within a vertical stack.

6 . The memory device of claim 1 , wherein the GAA structures include a conductive material having a top portion above a semiconductor material and a bottom material below the gate dielectric material.

7 . The memory device of claim 1 , wherein the channel material comprises a high doped semiconductor material to form a conductive body contact to the horizontally oriented access devices.

8 . The memory device of claim 1 , wherein a top electrode is separated from the bottom electrode by a cell dielectric.

9 . A memory device, comprising:
an array of vertically stacked memory cells, the array having horizontally oriented access devices and access lines and vertically oriented digit lines, comprising:
the horizontally oriented access devices having first source/drain regions and second source/drain regions separated by channel regions, and gates opposing the channel regions formed around the channel regions as gate all around (GAA) structures on a gate dielectric material;
horizontally oriented capacitor cells having a bottom electrode formed in electrical contact with the second source/drain regions; and
the vertically oriented digit lines are formed asymmetrically adjacent in electrical contact with the first source/drain regions.

10 . The memory device of claim 9 , further comprising the horizontally oriented access lines separated from the channel region by the gate dielectric.

11 . The memory device of claim 9 , further comprising horizontally oriented storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices.

12 . The memory device of claim 9 , further comprising the vertically oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices.

13 . The memory device of claim 9 , wherein channel material within the channel region comprises an insulator material.

14 . The memory device of claim 9 , wherein the vertically oriented digit lines are formed symmetrically, in vertical alignment, in electrical contact with the first source/drain regions.

15 . A memory device, comprising:
an array of vertically stacked memory cells, the array having horizontally oriented access devices and access lines and vertically oriented digit lines, comprising:
the horizontally oriented access devices having first source/drain regions and second source drain regions separated by channel regions, and gates opposing the channel regions formed around the channel region as gate all around (GAA) structures on a gate dielectric material; and
the horizontally oriented access devices formed in a vertical stack of materials formed on a silicon substrate, the vertical stack comprising repeating iterations of a first dielectric material, a second dielectric material, a semiconductor material, and a third dielectric material.

16 . The memory device of claim 15 , comprising:
storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices: and the vertically oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices.

17 . The memory device of claim 15 , comprising capacitor cells having a first horizontally oriented electrode electrically coupled to the first source/drain regions and a second electrode separated from the first horizontally oriented electrode by a cell dielectric.

18 . The memory device of claim 15 , wherein the gates opposing the channel regions provide a subthreshold voltage (sub-Vt) slope in a range of approximately 45 to 100 millivolts per decade (mV/dec).

19 . The memory device of claim 15 , wherein the vertically oriented digit lines comprise a highly phosphorus (P) doped (n+) poly-silicon germanium (SiGe) material.

20 . The memory device of claim 15 , wherein the vertically oriented digit lines comprise a tungsten (W) material formed on a titanium/titanium nitride (TiN) material which forms a titanium silicide with the first source/drain regions of the horizontally oriented access devices.

Assignees

• Micron Technology Inc

Inventors

• Lee Si-Woo
• Hwang Sangmin

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10B12/36 Primary

  the transistor being a FinFET · CPC title

• G11C11/4023

  using field effect transistors · CPC title

• H01L25/0657

  Electricity · mapped topic