Processing device, network node, client device, and methods thereof

Patent metadata

Field	Value
Publication number	US-2024171212-A1
Application number	US-202318512172-A
Country	US
Kind code	A1
Filing date	Nov 17, 2023
Priority date	May 4, 2017
Publication date	May 23, 2024
Grant date	—

Abstract

This disclosure relates to techniques for synchronization signals. The synchronization signal comprises a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with a Cell ID. The PSS sequence may be generated based on one of the first and the second sequences.

First claim

1 . A device, comprising:
a processor configured to: generate a primary synchronization signal (PSS) sequence that carries a second index N ID (2) of the PSS sequence; and generate a secondary synchronization signal (SSS) sequence that carries a first index N ID (1) of the SSS sequence, wherein the SSS sequence is based on a first binary sequence and a second binary sequence, wherein the second index N ID (2) of the PSS sequence is encoded to a first cyclic shift m 0 of the first binary sequence, and the first index N ID (1) of the SSS sequence is encoded to the first cyclic shift m 0 of the first binary sequence and a second cyclic shift m 1 of the second binary sequence.

2 . The device according to claim 1 , wherein the first index N ID (1) , the second index N ID (2) , the first cyclic shift m 0 , and the second cyclic shift m 1 satisfy:

m
0

=

g
⁡
(

N

ID
,
max

(
2
)

⁢

⌊

N
ID

(
1
)

L
′

⌋

+

N
ID

(
2
)

)

,
and

m
1

=

(

N
ID

(
1
)

⁢
mod
⁢

L
′

)

wherein:
g is an integer equal to or larger than 1;
L′ is a positive integer smaller or equal to a length L of the SSS sequence;
N ID (1) ∈{0, 1, 2, . . . , N ID,max (1) -1};
N ID (2) ∈{0, 1, . . . , N ID,max (2) -1};
└ . . . ┘ is a floor function; and
mod is a modulo operation.

3 . The device according to claim 2 , wherein the length L of the SSS sequence is 127, L′ is 112, N ID,max (2) is 3, N ID (2) ∈{0, 1, 2}, N ID,max (1) is 336, and N ID (1) ∈{0, 1, 2, . . . , 335}.

4 . The device according to claim 1 , wherein the first index N ID (1) , the second index N ID (2) , the first cyclic shift m 0 , and the second cyclic shift m 1 satisfy:

N
ID

(
1
)

=

m
1

+

L
′

⁢

⌊

m
0

gN

ID
,
max

(
2
)

⌋

,
and

N
ID

(
2
)

=

(

m
0

g

⁢
mod
⁢

N

ID
,
max

(
2
)

)

wherein:
g is an integer equal to or larger than 1;
L′ is a positive integer smaller or equal to a length L of the SSS sequence;
N ID (1) ∈{0, 1, 2, . . . , N ID,max (1) -1};
N ID (2) ∈{0, 1, . . . , N ID,max (2) -1};
└ . . . ┘ is a floor function; and
mod is a modulo operation.

5 . The device according to claim 1 , wherein the processor is configured to generate the SSS sequence based on the first binary sequence cyclically shifted by the first cyclic shift m 0 and the second binary sequence cyclically shifted by the second cyclic shift m 1 , the first binary sequence and the second binary sequence having a same length.

6 . The device according to claim 1 , wherein the first binary sequence and the second binary sequence are one in a group of:
m-sequences; or m-sequences resulting in that generated SSS sequences belong to one set of Gold sequences, wherein the generated SSS sequences include the SSS sequence.

7 . The device according to claim 1 , wherein one of the first binary sequence or second binary sequence utilized for generating the SSS sequence is a same binary sequence utilized for generating the PSS sequence.

8 . The device according to a claim 1 , wherein a first generator polynomial of the first binary sequence meets g 0 (x)=x 7 +x 4 +1, and a second generator polynomial of the second binary sequence meets g 1 (x)=x 7 +x+1.

9 . The device according to claim 1 , wherein the SSS sequence represented as d(k) satisfies:
d ( k )=1−2(( s 0 (( k+m 0 )mod L )+ s 1 (( k+m 1 )mod L ))mod 2),
wherein k∈{0, 1, 2, . . . , L-1}

Assignees

• Huawei Tech Co Ltd

Inventors

• Wang Peng
• Berggren Fredrik

Classifications

• H04J13/0074

  Code shifting or hopping · CPC title

• H04J11/0073 Primary

  Acquisition of primary synchronisation channel, e.g. detection of cell-ID within cell-ID group · CPC title

• H04B1/7083 Primary

  Cell search, e.g. using a three-step approach · CPC title

• H04B1/7093

  Matched filter type · CPC title

• H04J11/0076 Primary

  Acquisition of secondary synchronisation channel, e.g. detection of cell-ID group · CPC title