METHOD TO RETRIEVE TRANSACTION ADDRESS RESULTING IN AN UNCORRECTABLE PCIe ERROR

Patent metadata

Field	Value
Publication number	US-2024168842-A1
Application number	US-202318328927-A
Country	US
Kind code	A1
Filing date	Jun 5, 2023
Priority date	Nov 18, 2022
Publication date	May 23, 2024
Grant date	—

Abstract

A method to retrieve transaction address resulting in PCIe completion timeout includes monitoring a Peripheral Component Interconnect Express (PCIe) controller to detect a Completion Timeout (CTO) transmitted therefrom. A Master Identification (ID) of a Master and a transaction address of a transaction are stored in a configuration space, in response to detecting the CTO, wherein the transaction originates from the Master and the CTO is signaled in response to the transaction. The CTO is responded to with the Master identified by the Master ID in the configuration space.

First claim

What is claimed is:

1 . A method to retrieve transaction address resulting in PCIe completion timeout comprising:
monitoring a Peripheral Component Interconnect Express (PCIe) controller to detect a Completion Timeout (CTO) transmitted therefrom; storing in a configuration space, a Master Identification (ID) of a Master and a transaction address of a transaction, in response to detecting the CTO, wherein the transaction originates from the Master and the CTO is signaled in response to the transaction; and responding to the CTO with the Master identified by the Master ID in the configuration space.

2 . The method of claim 1 wherein the configuration space is configured by a Completion Timeout Reporting (CTOR) control register.

3 . The method of claim 2 wherein the CTOR enables storing the Master ID and the transaction address in the configuration space by a setting of an enable bit of the CTOR.

4 . The method of claim 2 wherein the CTOR configures a storage width of the transaction address in the configuration space by a setting of an address width bit of the CTOR.

5 . The method of claim 2 wherein the CTOR configures a length of a First In First Out (FIFO) register in the configuration space by a setting of a plurality of FIFO length bits of the CTOR, wherein the FIFO register is configured to store a plurality of error attributes received from the PCIe controller.

6 . The method of claim 1 further comprising storing a plurality of error attributes in the configuration space.

7 . The method of claim 1 wherein the response comprises terminating an application of the Master, wherein the transaction issues from the application.

8 . The method of claim 1 wherein the response comprises preventing further access to a memory space related to the transaction.

9 . The method of claim 1 wherein the transaction is a non-posted transaction and the CTO is transmitted by the PCIe controller in response to the PCIe controller not receiving a completion packet after a time duration.

10 . The method of claim 1 wherein performing the response with the Master comprises performing the response with an Advanced Reduced Instruction Set Computer Machine (ARM) core.

11 . A method to retrieve transaction address resulting in PCIe completion packet error comprising:
monitoring a Peripheral Component Interconnect Express (PCIe) controller to detect a completion packet error transmitted therefrom; storing in a configuration space, an error attribute of a transaction issued by a Master, in response to detecting the completion packet error; and responding to the completion packet error with the Master.

12 . The method of claim 11 wherein the error attribute comprises a Master Identification (ID) of the Master and a transaction address of the transaction.

13 . The method of claim 11 wherein the configuration space is configured by a Completion Timeout Reporting (CTOR) control register.

14 . The method of claim 11 wherein the response comprises terminating an application of the Master, wherein the transaction issues from the application.

15 . The method of claim 11 wherein the response comprises preventing further access to a memory space related to the transaction.

16 . A method to retrieve transaction address resulting in PCIe completion timeout comprising:
configuring a configuration space with a Completion Timeout Reporting (CTOR) control register; storing in the configuration space, a Master Identification (ID) of a Master and a transaction address of a transaction, in response to detecting a Completion Timeout (CTO) transmitted from a Peripheral Component Interconnect Express (PCIe) controller, wherein the transaction originates from the Master; and responding to the transaction with the Master identified by the Master ID in the configuration space.

17 . The method of claim 16 wherein the CTOR enables storing the Master ID and the transaction address in the configuration space by a setting of an enable bit of the CTOR.

18 . The method of claim 16 wherein the CTOR configures a storage width of the transaction address in the configuration space by a setting of an address width bit of the CTOR.

19 . The method of claim 16 wherein the CTOR configures a length of a First In First Out (FIFO) register in the configuration space by a setting of a plurality of FIFO length bits of the CTOR, wherein the FIFO register is configured to store a plurality of error attributes received from the PCIe controller.

20 . The method of claim 16 wherein the transaction is a non-posted transaction and the CTO is transmitted by the PCIe controller in response to the PCIe controller not receiving a completion packet after a time duration.

Assignees

• Nxp Usa Inc

Inventors

• Khan Wasim
• Singh Prabhjot
• Singh Deepak
• Sethi Varun

Classifications

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title