Layout pattern of static random access memory and the forming method thereof

Patent metadata

Field	Value
Publication number	US-2024161818-A1
Application number	US-202218071658-A
Country	US
Kind code	A1
Filing date	Nov 30, 2022
Priority date	Nov 10, 2022
Publication date	May 16, 2024
Grant date	—

Abstract

The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

First claim

What is claimed is:

1 . A layout pattern of a static random access memory (SRAM), at least comprising:
a substrate; a plurality of SRAM memory cells arranged on the substrate, wherein each SRAM memory cell comprises:
a plurality of fin structures positioned on the substrate;
a plurality of gate structures located on the substrate and span the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning the fin structure, and each transistor includes: two pull-up transistors (PU), two pull-down transistors (PD), which form a latch circuit, and two access transistors (PG) connected to the latch circuit;
wherein, in any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

2 . The layout pattern of the static random access memory (SRAM) according to claim 1 , further comprising a plurality of dummy fin structures located on the substrate, wherein the plurality of dummy fin structures are located between the PD fin structure and the adjacent PU fin structure, between the PU fin structure and the adjacent PU fin structure, between the PU fin structure and the adjacent PG fin structure, or between the PG fin structure and the adjacent PG fin structure.

3 . The layout pattern of the static random access memory (SRAM) according to claim 2 , wherein the dummy fin structure is not located between the PD fin structure and the adjacent PD fin structure.

4 . The layout pattern of the static random access memory (SRAM) according to claim 2 , wherein a height and a width of the dummy fin structure are smaller than a height and a width of the PG fin structure.

5 . The layout pattern of SRAM according to claim 2 , wherein a shortest distance between the PG fin structure and another adjacent PG fin structure is larger than a shortest distance between the PG fin structure and any adjacent dummy fin structure.

6 . The layout pattern of the static random access memory (SRAM) according to claim 2 , wherein a dummy fin structure is included between the PU fin structure and another adjacent PU fin structure, and another dummy fin structure is included between the PU fin structure and another adjacent PG fin structure.

7 . The layout pattern of the static random access memory (SRAM) according to claim 2 , wherein two dummy fin structures are included between the PG fin structure and another adjacent PG fin structure.

8 . The layout pattern of the static random access memory (SRAM) according to claim 1 , wherein in any SRAM memory cell, the PG fin structure and the PD fin structure are connected to each other and arranged in the same direction.

9 . A method for forming a layout pattern of a static random access memory (SRAM), at least comprising:
providing a substrate; forming a plurality of SRAM memory cells, which are arranged on the substrate, wherein each SRAM memory cell comprises:
a plurality of fin structures positioned on the substrate;
a plurality of gate structures located on the substrate and span the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning the fin structure, and the plurality of transistors include: two pull-up transistors (PU), two pull-down transistors (PD), which together form a latch circuit, and two access transistors (PG) connected to the latch circuit;
wherein, in any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

10 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 9 , further comprising forming a plurality of dummy fin structures on the substrate, wherein the plurality of dummy fin structures are located between the PD fin structure and the adjacent PU fin structure, between the PU fin structure and the adjacent PU fin structure, between the PU fin structure and the adjacent PG fin structure, or between the PG fin structure and the adjacent PG fin structure.

11 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 10 , wherein the dummy fin structure is not located between the PD fin structure and the adjacent PD fin structure.

12 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 10 , wherein a height and a width of the dummy fin structure are smaller than a height and a width of the PG fin structure.

13 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 10 , wherein a shortest distance between the PG fin structure and another adjacent PG fin structure is larger than a shortest distance between the PG fin structure and any dummy fin structure.

14 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 10 , wherein a dummy fin structure is included between the PU fin structure and another adjacent PU fin structure, and another dummy fin structure is included between the PU fin structure and another adjacent PG fin structure.

15 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 10 , wherein two dummy fin structures are included between the PG fin structure and another adjacent PG fin structure.

16 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 10 , wherein the method for forming the dummy fin structure further comprises:
forming a plurality of mandrel patterns on the substrate; forming a plurality of spacer patterns to surround each mandrel pattern; removing each mandrel pattern, leaving each spacer pattern; and performing an etching step to reduce the size of each spacer pattern, wherein the reduced spacer patterns are the dummy fin structures.

17 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 16 , wherein after forming each spacer pattern, at least one square spacer pattern is located between the PG fin structure and the adjacent PG fin structure.

18 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 17 , wherein the square spacer pattern is not located between the PD fin structure and the adjacent PD fin structure.

19 . The method for forming the layout pattern of the static random access memory (SRAM) according to claim 9 , wherein in any SRAM memory cell, the PG fin structure and the PD fin structure are connected to each other and arranged in the same direction.

Assignees

• United Microelectronics Corp

Inventors

• Huang Chun-Hsien
• Kuo Yu-Tse
• Wang Shu-Ru
• Huang Li-Ping
• Chen Yu-Fang
• Tseng Chun-Yen
• Chang Tzu-Feng
• Chang Chun-Chieh

Classifications

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/0243

  using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834

  comprising FinFETs · CPC title