Method for fault detection in safety mechanisms

Patent metadata

Field	Value
Publication number	US-2024160818-A1
Application number	US-202217985735-A
Country	US
Kind code	A1
Filing date	Nov 11, 2022
Priority date	Nov 11, 2022
Publication date	May 16, 2024
Grant date	—

Abstract

Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.

First claim

What is claimed is:

1 . A method for detecting faults in safety mechanisms, comprising:
generating safety mechanism test patterns; loading the safety mechanism test patterns into a pattern buffer coupled to the safety mechanisms comprised of a plurality of functional blocks; transmitting the safety mechanism test patterns to the safety mechanisms; and detecting safety mechanism errors in error handler circuitry.

2 . The method of claim 1 , wherein:
generating the safety mechanism test patterns includes generating a set of safety mechanism test patterns offline in an automatic test pattern generator.

3 . The method of claim 2 , further comprising storing the safety mechanism test patterns in external memory.

4 . The method of claim 2 , wherein the safety mechanism test patterns contain n words comprising m/p number of inputs to the safety mechanisms.

5 . The method of claim 2 , further comprising:
receiving configuration information and a compiled target netlist model in the automatic test pattern generator.

6 . The method of claim 1 , wherein:
generating the safety mechanism test patterns includes generating a set of safety mechanism test patterns in a hard-wired pattern generator.

7 . The method of claim 1 , further comprising:
retrieving the safety mechanism test patterns from the pattern buffer into an assembler; decoding the safety mechanism test patterns in the assembler; and configuring the safety mechanism test patterns in the assembler for an input interface of the functional blocks.

8 . The method of claim 1 , further comprising:
detecting test point value errors in the error handler circuitry; and notifying upstream logic when the test point value errors are detected.

9 . The method of claim 1 , wherein the safety mechanism test patterns are generated such that a safety mechanism test pattern count is reduced.

10 . The method of claim 1 , wherein one pattern buffer transmits test patterns to a plurality of safety mechanisms.

11 . A fault detection circuit, comprising:
one or more safety mechanisms; a pattern buffer coupled to the safety mechanisms and configured to receive safety mechanism test patterns; and error handler circuitry configured to detect errors in the safety mechanisms.

12 . The fault detection circuit of claim 11 , further comprising:
an automatic test pattern generator configured to compute the safety mechanism test patterns offline.

13 . The fault detection circuit of claim 12 , further comprising external memory configured to store the safety mechanism test patterns.

14 . The fault detection circuit of claim 12 , wherein the safety mechanism test patterns contain n words comprising m/p number of inputs to the safety mechanisms.

15 . The fault detection circuit of claim 12 , wherein the automatic test pattern generator is configured to receive configuration information and a compiled target netlist model.

16 . The fault detection circuit of claim 11 , further comprising:
a hard-wired pattern generator configured to generate the safety mechanism test patterns.

17 . The fault detection circuit of claim 11 , further comprising:
an assembler configured to retrieve the safety mechanism test patterns from the pattern buffer, decode the safety mechanism test patterns, and configure the safety mechanism test patterns for an input interface of a functional block of the safety mechanisms.

18 . The fault detection circuit of claim 11 , wherein the error handler circuitry is configured to detect test point value errors.

19 . The fault detection circuit of claim 11 , wherein the safety mechanism test patterns comprise values of a binary code.

20 . The fault detection circuit of claim 11 , wherein one pattern buffer is configured to transmit test patterns to a plurality of safety mechanisms.

Assignees

• Xilinx Inc

Inventors

• Venini Federico
• Tran David

Classifications

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/323

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title

• G06F2119/02

  Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] · CPC title