Display device

Patent metadata

Field	Value
Publication number	US-2024155896-A1
Application number	US-202318500113-A
Country	US
Kind code	A1
Filing date	Nov 2, 2023
Priority date	Nov 8, 2022
Publication date	May 9, 2024
Grant date	—

Abstract

A display device is disclosed that includes a substrate, a scan line disposed on the substrate and extending in a first direction, a data line disposed on the substrate and extending in a second direction crossing the first direction, a first transistor disposed on the substrate and including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, a second transistor including a second semiconductor layer electrically connected to the first transistor and the data line, and a second gate electrode overlapping the second semiconductor layer and electrically connected to the scan line, at least one inorganic insulating layer disposed on the substrate, and an auxiliary transistor disposed at an opposite side to the second transistor with a valley defined in the at least one inorganic insulating layer therebetween, wherein the auxiliary transistor is electrically connected to the data line and the scan line.

First claim

What is claimed is:

1 . A display device comprising:
a substrate; a scan line disposed on the substrate and extending in a first direction; a data line disposed on the substrate and extending in a second direction crossing the first direction; a first transistor disposed on the substrate and comprising a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer; a second transistor comprising a second semiconductor layer electrically connected to the first transistor and the data line, and a second gate electrode overlapping the second semiconductor layer and electrically connected to the scan line; at least one inorganic insulating layer disposed on the substrate; and an auxiliary transistor disposed at an opposite side to the second transistor with a valley defined in the at least one inorganic insulating layer therebetween, wherein the auxiliary transistor is electrically connected to the data line and the scan line.

2 . The display device of claim 1 , wherein the auxiliary transistor comprises an auxiliary semiconductor layer disposed at an opposite side to the second semiconductor layer with the valley therebetween and an auxiliary gate electrode electrically connected to the scan line and overlapping the auxiliary semiconductor layer.

3 . The display device of claim 2 , further comprising:
a first connection line configured to electrically connect the data line and the auxiliary semiconductor layer to each other, the first connection line overlapping the valley; and a second connection line configured to electrically connect the auxiliary semiconductor layer and the first semiconductor layer to each other, the second connection line overlapping the valley.

4 . The display device of claim 3 , wherein the first connection line and the second connection line comprise a same material.

5 . The display device of claim 3 , wherein the first connection line and the second connection line comprise a same material as the scan line.

6 . The display device of claim 2 , further comprising:
a first auxiliary scan line comprising the second gate electrode; and a second auxiliary scan line comprising the auxiliary gate electrode, wherein each of the first auxiliary scan line and the second auxiliary scan line is electrically connected to the scan line.

7 . The display device of claim 6 , wherein the first auxiliary scan line and the second auxiliary scan line are spaced apart from each other with the valley therebetween.

8 . The display device of claim 2 , wherein the auxiliary semiconductor layer comprises a same material as the second semiconductor layer.

9 . The display device of claim 1 , further comprising an organic insulating material at least partially filling the valley.

10 . A display device comprising:
a first sub-pixel circuit area and a second sub-pixel circuit area arranged adjacent to each other; a scan line extending in a first direction and passing through the first sub-pixel circuit area and the second sub-pixel circuit area; a data line extending in a second direction crossing the first direction and passing through the first sub-pixel circuit area; a first transistor comprising a first semiconductor layer disposed in the first sub-pixel circuit area and a first gate electrode overlapping the first semiconductor layer; a second transistor comprising a second semiconductor layer disposed in the first sub-pixel circuit area and electrically connected to the first transistor and the data line, and a second gate electrode overlapping the second semiconductor layer and electrically connected to the scan line; a valley disposed between the first sub-pixel circuit area and the second sub-pixel circuit area and defined in at least one inorganic insulating layer; and an auxiliary transistor comprising an auxiliary semiconductor layer disposed in the second sub-pixel circuit area and an auxiliary gate electrode overlapping the auxiliary semiconductor layer, wherein the auxiliary transistor is electrically connected to the data line and the scan line.

11 . The display device of claim 10 , further comprising:
a first connection line configured to electrically connect the data line and the auxiliary semiconductor layer to each other, the first connection line overlapping the valley; and a second connection line configured to electrically connect the auxiliary semiconductor layer and the first semiconductor layer to each other, the second connection line overlapping the valley.

12 . The display device of claim 11 , wherein the first connection line and the second connection line comprise a same material.

13 . The display device of claim 10 , further comprising:
a first auxiliary scan line comprising the second gate electrode; and a second auxiliary scan line comprising the auxiliary gate electrode, wherein each of the first auxiliary scan line and the second auxiliary scan line is electrically connected to the scan line.

14 . The display device of claim 13 , wherein the first auxiliary scan line and the second auxiliary scan line are spaced apart from each other with the valley therebetween.

15 . The display device of claim 10 , further comprising an organic insulating material at least partially filling the valley.

16 . The display device of claim 10 , wherein the auxiliary semiconductor layer comprises a same material as the second semiconductor layer.

17 . The display device of claim 15 , further comprising:
a first connection line disposed on the organic insulating material and configured to electrically connect the data line and the auxiliary semiconductor layer to each other, the first connection line overlapping the valley; and a second connection line disposed on the organic insulating material and configured to electrically connect the auxiliary semiconductor layer and the first semiconductor layer to each other, the second connection line overlapping the valley.

18 . The display device of claim 10 , further comprising a third transistor disposed in the first sub-pixel circuit area and electrically connected to the first transistor.

19 . The display device of claim 18 , wherein the third transistor comprises a third semiconductor layer comprising a different material from the first semiconductor layer and a third gate electrode overlapping the third semiconductor layer.

20 . The display device of claim 19 , wherein the first semiconductor layer and the third semiconductor layer are arranged on different layers.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Kwangwoo
• Shim Donghwan
• Lee Eonjoo
• Lee Jinyong
• Jang Cheol
• Jo Yongseon

Classifications

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title