Stacked microfeature devices and associated methods

Patent metadata

Field	Value
Publication number	US-2024153917-A1
Application number	US-202418412466-A
Country	US
Kind code	A1
Filing date	Jan 12, 2024
Priority date	Aug 29, 2003
Publication date	May 9, 2024
Grant date	—

Abstract

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

First claim

We claim:

1 . A microfeature device assembly, comprising:
a lower die having a first active surface and a first set of bond pads at the first active surface, wherein the first set of bond pads comprises at least one subset having a lower device bond pad, an intermediate bond pad, and a wirebond pad coupled at the first active surface; an upper die carried by the lower die and having a second active surface and a second set of bond pads at the second active surface, wherein the second set of bond pads comprises an upper device bond pad vertically aligned with the intermediate bond pad; and a conductive structure electrically coupling the upper device bond pad to the intermediate bond pad.

2 . The microfeature device assembly of claim 1 wherein the lower device bond pad is a first lower device bond pad, wherein the wirebond pad is a first wirebond pad, and wherein the first set of bond pads further comprises a second lower device bond pad coupled to a second wirebond pad at the first active surface independent from the at least one subset.

3 . The microfeature device assembly of claim 2 wherein signals received at the first wirebond pad are routed to both the first lower device bond pad and the upper device bond pad, and wherein signals received at the second wirebond pad are routed to only the second lower device bond pad.

4 . The microfeature device assembly of claim 1 wherein the intermediate bond pad is a first intermediate bond pad, wherein the wirebond pad is a first wirebond pad, and wherein the first set of bond pads further comprises a second intermediate bond pad coupled to a second wirebond pad at the first active surface independent from the at least one subset.

5 . The microfeature device assembly of claim 4 wherein the upper device bond pad is a first upper device bond pad, and wherein the second set of bond pads further comprises a second upper device bond pad vertically aligned with the second intermediate bond pad.

6 . The microfeature device assembly of claim 1 , further comprising a support assembly carrying the lower die and a wirebond coupling the wirebond pad to the support assembly.

7 . The microfeature device assembly of claim 1 wherein the lower device bond pad is a first lower device bond pads from a plurality of lower device bond pads aligned along a first axis, and wherein the intermediate bond pad is a first intermediate bond pads from a plurality of intermediate bond pads aligned along a second axis.

8 . A semiconductor device assembly, comprising:
a first die having a first bond pad surface, wherein the first bond pad surface includes a plurality of first device bond pads, a plurality of intermediate bond pads, and a plurality of wirebond pads, and wherein:
at least one pair of bond pads is jointly coupled to an individual wirebond pad from the plurality of wirebond pads, wherein the at least one pair of bond pads comprises an individual first device bond pad from the plurality of first device bond pads and an individual intermediate bond pad from the plurality of intermediate bond pads;
a second die carried by the first die and having a second bond pad surface facing the first bond pad surface, wherein the second bond pad surface includes a plurality of second device bond pads each vertically aligned with a corresponding one of the plurality of intermediate bond pads; and a plurality of conductive members each disposed on one of the plurality of intermediate bond pads and individually coupling the plurality of intermediate bond pads to the plurality of second device bond pads.

9 . The semiconductor device assembly of claim 8 , wherein the individual wirebond pad is a first individual wirebond pad, and wherein:
at least one of the plurality of first device bond pads is independently coupled to a second individual wirebond pad from the plurality of wirebond pads; and at least one of the plurality of intermediate bond pads is independently coupled to a third individual wirebond pad from the plurality of wirebond pads.

10 . The semiconductor device assembly of claim 9 wherein signals arriving at the second individual wirebond pad are communicated only to the first die, and wherein signals arriving at the third individual wirebond pad are communicated only to the second die.

11 . The semiconductor device assembly of claim 8 wherein each of the plurality of first device bond pads is coupled to one of the plurality of wirebond pads, and wherein each of the plurality of intermediate bond pads is coupled to one of the plurality of wirebond pads.

12 . The semiconductor device assembly of claim 8 wherein each of the plurality of first device bond pads is aligned along a first axis, and wherein each of the plurality of intermediate bond pads is aligned along a second axis.

13 . The semiconductor device assembly of claim 8 wherein the first bond pad surface has a centerline, and wherein the plurality of intermediate bond pads are positioned in a mirror image about the centerline relative to the plurality of first device bond pads.

14 . A stacked semiconductor device assembly, comprising:
a support member; a first die carried by the support member and having a first active surface, wherein the first active surface includes:
a plurality of wirebond pads; and
a first set of bond pads, wherein the first set of bond pads is electrically coupled to the plurality of wirebond pads via a plurality of couplers at the first active surface;
a second die carried by the first die and having a second active surface, wherein the second active surface includes a second set of bond pads, and wherein each bond pad in the second set of bond pads is vertically aligned with a corresponding bond pad from the first set of bond pads; and a conductive structure electrically coupling each of the bond pads in the second set of bond pads to the corresponding bond pad from the first set of bond pads.

15 . The stacked semiconductor device assembly of claim 14 wherein the first set of bond pads includes a device bond pad and an intermediate bond pad jointly coupled to an individual wirebond pad from the plurality of wirebond pads.

16 . The stacked semiconductor device assembly of claim 14 wherein the first set of bond pads includes two or more device bond pads and two or more intermediate bond pads, and wherein at least one pair of a device bond pad and an intermediate pad are jointly coupled to an individual wirebond pad from the plurality of wirebond pads.

17 . The stacked semiconductor device assembly of claim 16 wherein each bond pad in the second set of bond pads is vertically aligned with a corresponding intermediate bond pad.

18 . The stacked semiconductor device assembly of claim 16 wherein at least one of the two or more device bond pads is coupled to an individual wirebond pad independent from the two or more intermediate bond pads.

19 . The stacked semiconductor device assembly of claim 14 wherein each bond pad in the first set of bond pads is aligned along an axis.

20 . The stacked semiconductor device assembly of claim 14 wherein the first set of bond pads includes two or more device bond pads and two or more intermediate bond pads, wherein each bond pad in the second set of bond pads is vertically aligned with a corresponding intermediate bond pad, and wherein at least one of the two or more intermediate bond pads is coupled to an individual wirebond pad independent from the two or more device bond pads.

Assignees

• Micron Technology Inc

Inventors

• Heng Mung Suan
• Tan Kok Chua
• Leong Vince Chan Seng
• Johnson Mark S

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/721

  of bump connectors · CPC title