Semiconductor package, semiconductor device, and power conversion device
US-2024055357-A1 · Feb 15, 2024 · US
Semiconductor device
US2024145349A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2024145349-A1 |
| Application number | US-202318474325-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 26, 2023 |
| Priority date | Nov 2, 2022 |
| Publication date | May 2, 2024 |
| Grant date | — |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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- CPC / IPC classifications
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- Citations and related patents
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Abstract
Official abstract text for this publication.
A semiconductor device includes: a first element for one of upper and lower arm circuits; a second element for the other of the upper and lower arm circuits; a first wiring having a first mounting portion on which the first element is disposed and a first power supply terminal portion connected with the first mounting portion; a second wiring having a second mounting portion on which the second element is disposed and an output terminal portion connected with the second mounting portion; a clip configured to electrically connect a main electrode of the first element and the second mounting portion; and a third wiring having a connection portion to which a main electrode of the second element is connected and a second power supply terminal portion connected with the connection portion. The third wiring is extended parallel to the first wiring and the clip.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device for upper and lower arm circuits of at least one phase, comprising: a plurality of semiconductor elements including a first element for one arm of the upper and lower arm circuits and a second element for another arm of the upper and lower arm circuits, each having a first main electrode provided on one surface and a second main electrode provided on a back surface opposite to the one surface in a thickness direction; a first wiring having a first mounting portion on which the first element is disposed and to which a first main electrode of the first element is connected, and a first power supply terminal portion connected to the first mounting portion; a second wiring having a second mounting portion on which the second element is disposed and to which a first main electrode of the second element is connected, and an output terminal portion continuous with the second mounting portion, the first mounting portion and the second mounting portion being arranged in one direction orthogonal to the thickness direction; a clip configured to electrically connect the second main electrode of the first element and the second mounting portion; and a third wiring having a connection portion to which a second main electrode of the second element is connected and a second power supply terminal portion connected to the connection portion, wherein the third wiring extends parallel to the first wiring and the clip. 2 . The semiconductor device according to claim 1 , wherein the third wiring extends in parallel over an entire length of the clip in a plan view corresponding to the thickness direction. 3 . The semiconductor device according to claim 1 , wherein the third wiring extends parallel to the first wiring and the clip, while the third wiring faces the first wiring and the clip in the thickness direction. 4 . The semiconductor device according to claim 1 , wherein the third wiring extends parallel to the first wiring and the clip while the third wiring faces the first wiring and the clip in a direction orthogonal to both an arrangement direction of the first mounting portion and the second mounting portion and the thickness direction. 5 . The semiconductor device according to claim 1 , wherein the clip is a first clip, and the third wiring includes a second clip including the connection portion, and a terminal including the second power supply terminal portion and connected to the second clip.
Assignees
Inventors
Classifications
between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink · CPC title
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
between laterally-adjacent chips · CPC title
of outermost layers of multilayered strap connectors, e.g. material of a coating · CPC title
comprising metals or metalloids, e.g. silver · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2024145349A1 cover?
- A semiconductor device includes: a first element for one of upper and lower arm circuits; a second element for the other of the upper and lower arm circuits; a first wiring having a first mounting portion on which the first element is disposed and a first power supply terminal portion connected with the first mounting portion; a second wiring having a second mounting portion on which the second…
- Who is the assignee on this patent?
- Denso Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W70/481. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu May 02 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).