Computing system and trusted computing method

Patent metadata

Field	Value
Publication number	US-2024143851-A1
Application number	US-202318189381-A
Country	US
Kind code	A1
Filing date	Mar 24, 2023
Priority date	Nov 2, 2022
Publication date	May 2, 2024
Grant date	—

Abstract

A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

First claim

What is claimed is:

1 . A computing system, comprising:
a processor, including a normal core, and a trusted core for trusted computing; a system memory, providing a normal memory, and an isolated memory for the trusted computing; and a chipset, coupled to the processor, the system memory, and a plurality of peripherals for communication among the processor, the system memory, and the plurality of peripherals, wherein: the isolated memory stores a security interrupt descriptor table to correspond to security interrupts triggered by security peripherals; a first register of the trusted core stores a first address pointing to the security interrupt descriptor table; a local advanced programmable interrupt controller of the trusted core includes an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset; when producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the security interrupt descriptor table indicated by the first register, to get a target security interrupt descriptor for execution of a corresponding interrupt program.

2 . The computing system as claimed in claim 1 , wherein:
the normal memory stores a normal interrupt descriptor table to correspond to normal interrupts triggered by normal peripherals; a second register of the trusted core stores a second address pointing to the normal interrupt descriptor table; when producing an arbitration result showing that a target interrupt is a normal interrupt, the interrupt arbiter outputs a normal interrupt request and a normal interrupt vector to trigger the trusted core to search the normal interrupt descriptor table indicated by the second register, to get a target normal interrupt descriptor for execution of a corresponding interrupt program.

3 . The computing system as claimed in claim 1 , wherein:
the chipset transfers a message signaled interrupt received from a security peripheral to the processor, to inform the interrupt arbiter of the local advanced programmable interrupt controller of the trusted core that a security interrupt is issued by the security peripheral.

4 . The computing system as claimed in claim 3 , wherein:
the message signaled interrupt issued by the security peripheral is marked by the chipset for a host interface advanced programmable interrupt controller on the processor to recognize that the message signaled interrupt is issued by the security peripheral and, accordingly, the host interface advanced programmable interrupt controller transfers the message signaled interrupt to the interrupt arbiter of the local advanced programmable interrupt controller of the trusted core.

5 . The computing system as claimed in claim 4 , wherein:
the chipset changes base address information carried in the message signaled interrupt to a specific value to show that the message signaled interrupt is issued by the security peripheral.

6 . The computing system as claimed in claim 1 , wherein:
the chipset includes a security interrupt controller; each security peripheral has a peripheral-chipset pin coupled to the security interrupt controller to transfer a security interrupt from the security peripheral to the security interrupt controller; and the security interrupt controller is further coupled to the processor and, in response to a security interrupt received from a security peripheral, the security interrupt controller informs the interrupt arbiter of the local advanced programmable interrupt controller of the trusted core that the security interrupt is issued.

7 . The computing system as claimed in claim 6 , wherein the security interrupt controller comprises:
a programmable interrupt controller, arbitrating between security interrupts received from the security peripherals connected to the security interrupt controller and, according to an arbitration result, generating a security interrupt request and a security interrupt vector; and a security interrupt processing unit, coupled between the programmable interrupt controller and the processor, wherein the security interrupt processing unit is coupled to the processor via chipset-processor pins corresponding to the different security peripherals and, according to the security interrupt vector received from the programmable interrupt controller, the security interrupt processing unit asserts a corresponding chipset-processor pin.

8 . The computing system as claimed in claim 7 , wherein:
the chipset-processor pins are coupled to the local advanced programmable interrupt controller of the trusted core.

9 . The computing system as claimed in claim 6 , wherein the security interrupt controller comprises:
a programmable interrupt controller, arbitrating between security interrupts received from the security peripherals connected to the security interrupt controller and, according to an arbitration result, generating a security interrupt request and a security interrupt vector; and a security interrupt processing unit, coupled between the programmable interrupt controller and the processor, wherein the security interrupt processing unit transfers the security interrupt vector received from the programmable interrupt controller to the processor.

10 . The computing system as claimed in claim 9 , wherein:
the security interrupt vector that the security interrupt processing unit transfers to the processor is received by the local advanced programmable interrupt controller of the trusted core.

11 . A trusted computing method, comprising:
operating an interrupt arbiter provided by a trusted core of a processor to arbitrate between peripheral interrupts received from a chipset; and when the interrupt arbiter produces an arbitration result showing that a target interrupt is a security interrupt, operating the interrupt arbiter to output a security interrupt request and a security interrupt vector to trigger the trusted core to search a security interrupt descriptor table indicated by a first register, to get a target security interrupt descriptor for execution of a corresponding interrupt program.

12 . The trusted computing method as claimed in claim 11 , further comprising:
when the interrupt arbiter produces an arbitration result showing that a target interrupt is a normal interrupt, operating the interrupt arbiter to output a normal interrupt request and a normal interrupt vector to trigger the trusted core to search a normal interrupt descriptor table indicated by a second register, to get a target normal interrupt descriptor for execution of a corresponding interrupt program.

13 . The trusted computing method as claimed in claim 11 , further comprising:
operating the chipset to transfer a message signaled interrupt received from a security peripheral to the processor, to inform the interrupt arbiter of the trusted core that a security interrupt is issued by the security peripheral.

14 . The trusted computing method as claimed in claim 13 , wherein:
the message signaled interrupt issued by the security peripheral is marked by the chipset for a host interface advanced programmable interrupt controller on the processor to recognize that the message signaled interrupt is issued by the security peripheral and, accordingly, the host interface advanced programmable interrupt controller transfers the message signaled interrupt to the interrupt arbiter of the trusted core.

15 . The trusted computing method as claimed in claim 14 , wherein:
the chipset change

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Huang Zhenhua
• Guan Yingbing
• Li Yanting

Classifications

• G06F21/85 Primary

  interconnection devices, e.g. bus-connected or in-line devices · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title