Array substrate, opposite substrate, and display panel

Patent metadata

Field	Value
Publication number	US-2024142819-A1
Application number	US-202117770820-A
Country	US
Kind code	A1
Filing date	May 21, 2021
Priority date	May 21, 2021
Publication date	May 2, 2024
Grant date	—

Abstract

An array substrate, an opposite substrate and a display panel are provided. The array substrate comprises: a display region and a periphery region surrounding the display region, wherein the display region comprises a plurality of pixel regions, and each of the pixel regions comprises a reflective region and a transmissive region; the reflective region comprises a driving signal outputting layer, a segment gap layer, a passivation layer and a reflective layer, the reflective layer is coupled to the driving signal outputting layer to enable both the reflective layer and the driving signal outputting layer to function as a reflective region driving electrode; the transmissive region comprises a first electrode layer, the first electrode layer is coupled to the driving signal outputting layer, the passivation layer extends to the transmissive region, and the passivation layer is arranged between the first electrode layer and a first base of the display substrate.

First claim

1 . An array substrate comprising: a display region and a periphery region surrounding the display region, wherein the display region comprises a plurality of pixel regions, and each of the pixel regions comprises a reflective region and a transmissive region;
the reflective region comprises a driving signal outputting layer, a segment gap layer, a passivation layer and a reflective layer, the reflective layer is coupled to the driving signal outputting layer to enable both the reflective layer and the driving signal outputting layer to function as a reflective region driving electrode; the transmissive region comprises a first electrode layer, the first electrode layer is coupled to the driving signal outputting layer, the passivation layer extends to the transmissive region, and the passivation layer is arranged between the first electrode layer and a first base of the display substrate.

2 . The array substrate according to claim 1 , wherein there is a maximum segment gap d1 between a surface of the reflective layer distal to the first base and a surface of a portion of the first electrode layer distal to the first base, and the portion of the first electrode layer is arranged at the transmissive region, where 2 μm≤d1≤3 μm.

3 . The array substrate according to claim 1 , wherein the segment gap layer comprises a buffer layer and an OverCoating (OC) layer, and the buffer layer is arranged between the OC layer and the first base.

4 . The array substrate according to claim 1 , wherein the array substrate further comprises a driving electrode arranged in the reflective region, and the reflective layer further functions as the driving electrode.

5 . The array substrate according to claim 1 , wherein the reflective region further comprises a gate metal layer, a gate insulation layer and an active layer; the gate metal layer, the gate insulation layer and the active layer are laminated on one on another in a direction away from the first base, the driving signal outputting layer is arranged at a side of the active layer distal to the first base; the gate metal layer, the gate insulation layer, the active layer and the driving signal outputting layer are capable of forming a thin-film transistor, the driving signal outputting layer functions as an output electrode of the thin-film transistor;
the gate insulation layer extends to the transmissive region and the periphery region; the passivation layer extends to the periphery region.

6 . The array substrate according to claim 5 , wherein the periphery region comprises:
a common signal outputting layer and a common signal transmission layer that are coupled to each other; the common signal outputting layer is arranged at a side of the passivation layer distal to the first base, and the common signal transmission layer is arranged between the passivation layer and the first base.

7 . The array substrate according to claim 6 , wherein the common signal outputting layer and the first electrode layer are arranged at a same layer and made of a same material, and the common signal transmission layer and the gate metal layer are arranged at a same layer and made of a same material.

8 . An opposite substrate comprising: a display region and a periphery region surrounding the display region, wherein the opposite substrate further comprises a second base, a color resist layer, a common electrode, and a wall structure, wherein the color resist layer, the common electrode, and the wall structure are arranged on the color resist layer;
wherein both the color resist layer and the common electrode are capable of extending from the display region to the periphery region; and the wall structure is arranged in the periphery region, and the wall structure comprises an inner wall pattern and an outer wall pattern, the inner wall pattern is arranged between the display region and the outer wall pattern, the inner wall pattern and the outer wall pattern are at least partially staggered to form a passage from the display region to a side of the wall structure distal to the display region.

9 . The opposite substrate according to claim 8 , wherein the periphery region comprises a corner region and a straight region;
the inner wall pattern comprises a first corner wall pattern and a first straight wall pattern; the outer wall pattern comprises a second corner wall pattern and a second straight wall pattern; and in at least one straight region, the first straight wall pattern and the second straight wall pattern are arranged alternately in an extension direction of the straight region.

10 . The opposite substrate according to claim 9 , wherein
in a same straight region, an orthographic projection of the first straight wall pattern in a first direction partially overlaps an orthographic projection of the second straight wall pattern in the first direction partially overlap, and the first direction is parallel to an extension direction of the first straight wall pattern and an extension direction of the second straight wall pattern.

11 . The opposite substrate according to claim 10 , wherein in the same straight region, there is an overlapped portion of the orthographic projection of the first straight wall pattern in the first direction and the orthographic projection of the second straight wall pattern in the first direction, and a length a1 of the overlapped portion satisfies: 18 μm≤a1≤25 μm;
in an extension direction parallel to the first straight wall pattern, a length a2 of the first straight wall pattern satisfies: 480 μm≤a2≤520 μm;
in an extension direction parallel to the second straight wall pattern, a length a2 of the second straight wall pattern satisfies: 480 μm≤a3≤520 μm;
in an extension direction parallel to the first straight wall pattern, a distance a4 between the adjacent first straight wall patterns satisfies: 440 μm≤a4≤480 μm;
in an extension direction parallel to the second straight wall pattern, a distance a5 between the adjacent second straight wall patterns satisfies: 440 μm a5≤480 μm;
a minimum distance a6 between the first corner wall pattern and the display region satisfies: 50 μm≤a6≤350 μm;
in a direction perpendicular to the first direction, a distance a7 between a border of the first straight wall pattern proximate to the display region and a border of the second straight wall pattern distal to the display region satisfies: 40 μm≤a7≤60 μm;
in a same corner region, an extension direction of the first corner wall pattern and an extension direction of the second corner wall pattern are same; and in an extension direction perpendicular to the first corner wall pattern, a distance a8 between a border of the first corner wall pattern proximate to the display region and a border of the second corner wall pattern distal to the display region satisfies: 40 μm≤a8≤60 μm; and
the second corner wall pattern is adjacent to the first straight region and the second straight region, a first end of the second corner wall pattern is proximate to the first straight region, and a second end of the second corner wall pattern is proximate to the second straight region; a distance a9 between the first end and a border of the second straight region distal to the display region satisfies: 3 mm≤a9≤3.4 mm; a distance a10 between the second end and the first straight region distal to a border of the display region satisfies: 2.8 mm≤a10≤3.2 mm.

12 . A display panel comprising the array substrate according to claim 1 and an opposite substrate comprising a display region and a periphery region surrounding the display region, wherein the opposite substrate further comprises a second base, a color resist layer, a common electrode, and a wall stru

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wu Xiaojuan
• Wang Jiaxing
• Zhong Xuan
• Yuan Hongliang
• Bi Yao
• Duan Jinshuai
• Qu Feng
• Zhao Xinxin
• Wang Jian

Classifications

• G02F1/133553 Primary

  Reflecting elements (associated to illuminating devices G02F1/133605) · CPC title

• G02F1/1339 Primary

  Gaskets; Spacers; Sealing of cells · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/1337

  Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title

• G02F1/133514

  Colour filters · CPC title