N-type 2d transition metal dichalcogenide (tmd) transistor

Patent metadata

Field	Value
Publication number	US-2024136429-A1
Application number	US-202217969232-A
Country	US
Kind code	A1
Filing date	Oct 19, 2022
Priority date	Oct 19, 2022
Publication date	Apr 25, 2024
Grant date	—

Abstract

A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.

First claim

What is claimed is:

1 . A transition metal dichalcogenide (TMD) transistor, comprising:
a substrate having a top portion that is an insulating layer; an n-type two-dimensional (2D) TMD layer on the insulating layer; a metal source electrode, a metal drain electrode, and a gate dielectric on the n-type 2D TMD layer; and a metal gate electrode on top of the gate dielectric, wherein the metal gate electrode is between the metal source electrode and the metal drain electrode.

2 . The TMD transistor according to claim 1 wherein the substrate contains a non-TMD transistor comprising silicon, silicon germanium, a III-V material, or a II-VI material, or any combination thereof.

3 . The TMD transistor according to claim 2 wherein the substrate further comprises a back end of line (BEOL) metal line above the non-TMD transistor.

4 . The TMD transistor according to claim 1 wherein the n-type 2D TMD layer comprises MoS 2 or WS 2 .

5 . The TMD transistor according to claim 1 wherein the n-type 2D TMD layer has a thickness in the range of 1 to 3 monolayers.

6 . The TMD transistor according to claim 1 wherein the n-type 2D TMD layer is doped with aluminum.

7 . The TMD transistor according to claim 1 wherein both the metal source electrode and the metal drain electrode comprises Sc or Ni, or a combination thereof.

8 . The TMD transistor according to claim 1 wherein a lower portion of both the metal source electrode and the metal drain electrode comprises aluminum.

9 . The TMD transistor according to claim 1 wherein the gate dielectric structure comprises an insulator selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, silicon oxide, silicon oxynitride, and any combination thereof.

10 . The TMD transistor according to claim 9 wherein the gate dielectric structure comprises a dielectric layer having the aluminum oxide in contact with the n-type 2D TMD layer.

11 . The TMD transistor according to claim 1 wherein the gate dielectric structure extends over a region of the n-type 2D TMD layer between the metal source electrode and the metal drain electrode and along sidewalls of the metal source electrode and the metal drain electrode.

12 . The TMD transistor according to claim 1 wherein the metal gate electrode contains Ni, Ti, or a combination of Ni and Ti.

13 . A method for forming a transition metal dichalcogenide (TMD) transistor comprising:
providing a substrate having a top layer that is insulating; forming a two-dimensional (2D) TMD layer onto the substrate; depositing aluminum on the 2D TMD layer; forming a metal source electrode and a metal drain electrode on the 2D TMD layer; forming a gate dielectric on the 2D TMD layer; and forming a metal gate electrode on the gate dielectric and between the metal source electrode and the metal drain electrode.

14 . The method according to claim 13 wherein the substrate contains a non-TMD transistor comprising silicon, silicon germanium, a III-V material, or a II-VI material, or any combination thereof.

15 . The method according to claim 14 wherein the substrate further comprises a back end of line (BEOL) metal line above the non-TMD transistor.

16 . The method according to claim 13 wherein the 2D TMD layer comprises MoS 2 or WS 2 .

17 . The method according to claim 13 wherein the 2D TMD layer has a thickness in the range of 1 to 3 monolayers.

18 . The method according to claim 13 wherein both the metal source electrode and the metal drain electrode comprises Sc or Ni, or a combination thereof.

19 . A two-dimensional (2D) transistor, comprising:
a substrate; a 2D transition metal disulfide layer doped with aluminum and located on top of the substrate; a metal source electrode and a metal drain electrode on the 2D transition metal disulfide layer; a gate dielectric on the 2D transition metal disulfide layer; and a metal gate electrode on the gate dielectric; wherein: the substrate contains (1) a non-transition metal dichalcogenide (TMD) transistor comprising silicon, silicon germanium, a III-V material, or a II-VI material, (2) a BEOL metal line above the non-TMD transistor, and (3) an insulating top layer; and the metal gate electrode is between the metal source electrode and the metal drain electrode.

20 . The 2D transistor according to claim 19 wherein both the metal source electrode and the metal drain electrode comprises Sc or Ni, or a combination thereof.

21 . The 2D transistor according to claim 19 wherein an electrically conductive path exists between at least one electrode of the 2D transistor and the BEOL metal line.

22 . The 2D transistor according to claim 19 wherein the 2D transition metal disulfide layer comprises MoS 2 or WS 2 and has a thickness in the range of 1 to 3 monolayers.

23 . The 2D transistor according to claim 19 wherein a lower portion of both the metal source electrode and the metal drain electrode comprises aluminum.

24 . The 2D transistor according to claim 19 wherein the gate dielectric comprises a dielectric layer that includes aluminum oxide in contact with the 2D transition metal disulfide layer.

25 . The 2D transistor according to claim 19 wherein the gate dielectric extends over a region of the 2D transition metal disulfide layer between the metal source electrode and the metal drain electrode and along sidewalls of the metal source electrode and the metal drain electrode.

Assignees

• Hrl Lab Llc

Inventors

• Son Kyung-Ah
• Moon Jeong-Sun
• Seo Hwa Chang

Classifications

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/2913

  being Group IIB-VIA materials · CPC title

• H10P14/2907

  being Group IIIA-VA materials · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3452

  Microstructure · CPC title