Technologies for accelerated quic packet processing with hardware offloads

Patent metadata

Field	Value
Publication number	US-2024121225-A1
Application number	US-202318514713-A
Country	US
Kind code	A1
Filing date	Nov 20, 2023
Priority date	Mar 16, 2018
Publication date	Apr 11, 2024
Grant date	—

Abstract

Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.

First claim

1 . One or more non-transitory computer-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause one or more processors to:
configure circuitry of a network interface controller to perform segmentation of a payload of a Quick User Datagram Protocol (UDP) Internet Connection (QUIC) packet to generate payload segments and to perform encryption of the payload segments prior to transmission of the QUIC payload segments.

2 . The one or more computer-readable storage media of claim 1 , wherein the QUIC packet comprises a UDP packet that includes a QUIC header and the payload, and wherein the QUIC packet is associated with a QUIC connection.

3 . The one or more computer-readable storage media of claim 1 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the one or more processors to:
program the network interface controller with an encryption key associated with a QUIC connection, wherein the QUIC packet is associated with a QUIC connection.

4 . The one or more computer-readable storage media of claim 3 , wherein the circuitry is to perform encryption of the payload based on the encryption key.

5 . The one or more computer-readable storage media of claim 3 , wherein the circuitry is to perform encryption of the payload based on an application-layer encryption protocol.

6 . (canceled)

7 . The one or more computer-readable storage media of claim 1 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the one or more processors to:
program the network interface controller to: include a copy of a QUIC header of the QUIC packet in at least one of the segmented QUIC packets and update a packet number of the QUIC header of at least one of the segmented QUIC packets.

8 . An apparatus comprising:
a network interface controller comprising:
a direct memory access (DMA) circuitry;
a host interface;
a network interface; and
circuitry to segment a payload of a Quick User Datagram Protocol (UDP) Internet Connection (QUIC) packet and generate payload segments and to perform encryption of the payload segments prior to transmission of the QUIC payload segments.

9 . The apparatus of claim 8 , wherein the QUIC packet comprises a UDP packet that includes a QUIC header and the payload, and wherein the QUIC packet is associated with a QUIC connection.

10 . The apparatus of claim 8 , wherein the circuitry is to encrypt the payload based on an encryption key associated with a QUIC connection, wherein the QUIC packet is associated with a QUIC connection.

11 . The apparatus of claim 8 , wherein the circuitry is to encrypt the payload based on an encryption key associated with a QUIC connection, wherein the circuitry is to perform encryption of the payload based on an application-layer encryption protocol.

12 . (canceled)

13 . The apparatus of claim 8 , wherein to segment the QUIC packet into a plurality of segmented QUIC packets comprises:
include a copy of a QUIC header of the QUIC packet to at least one of the segmented QUIC packets and update a packet number of the QUIC header of the segmented QUIC packets.

14 . (canceled)

15 . (canceled)

16 . A method comprising:
segmenting a payload of a Quick User Datagram Protocol (UDP) Internet Connection (QUIC) packet; performing encryption of the payload segments; and transmitting the segmented QUIC packets with encrypted payloads.

17 . The method of claim 16 , wherein the encrypting the payload comprises encrypting the payload based on an encryption key associated with a QUIC connection and based on an application-layer encryption protocol.

18 . (canceled)

19 . The method of claim 6 , wherein segmenting the QUIC packet into a plurality of segmented QUIC packets comprises
including a copy of a QUIC header of the QUIC packet in at least one of the segmented QUIC packets and updating a packet number of the QUIC header of the segmented QUIC packets.

20 . (canceled)

Assignees

• Intel Corp

Inventors

• Deval Manasi
• Bowers Gregory

Classifications

• H04L63/0428 Primary

  wherein the data content is protected, e.g. by encrypting or encapsulating the payload · CPC title

• H04L9/088 Primary

  Usage controlling of secret information, e.g. techniques for restricting cryptographic keys to pre-authorized uses, different access levels, validity of crypto-period, different key- or password length, or different strong and weak cryptographic algorithms (network architectures or network communication protocols for using time-dependent keys in a packet data network H04L63/068) · CPC title

• H04L63/06

  for supporting key management in a packet data network (cryptographic mechanisms or cryptographic arrangements for key management H04L9/08) · CPC title

• H04L69/161

  Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields · CPC title

• H04L69/164

  Adaptation or special uses of UDP protocol · CPC title