Joint sample rate offset and symbol timing offset correction

Patent metadata

Field	Value
Publication number	US-2024121147-A1
Application number	US-202318376782-A
Country	US
Kind code	A1
Filing date	Oct 4, 2023
Priority date	Oct 5, 2022
Publication date	Apr 11, 2024
Grant date	—

Abstract

A receiver has a sample rate converter that outputs samples of orthogonal frequency division multiplexing symbols. The receiver includes a fast Fourier transform engine that receives the samples and converts them into a plurality of frequency domain sub-carriers. A timing control circuit generates a timing error and controls the sample rate converter to adjust a sample rate of the orthogonal frequency division multiplexing symbols based at least in part on the timing error.

First claim

What is claimed is:

1 . A receiver comprising:
a sample rate converter configured to output one or more samples of one or more orthogonal frequency division multiplexing symbols; a fast Fourier transform engine configured to receive the one or more samples and convert each of the one or more samples into a plurality of frequency domain sub-carriers; and a timing control circuit configured to generate a timing error and control the sample rate converter to adjust a sample rate of the one or more orthogonal frequency division multiplexing symbols based at least in part on the timing error.

2 . The receiver of claim 1 further comprising a buffer configured to store the one or more samples of one or more orthogonal frequency division multiplexing symbols, the fast Fourier transform engine configured to receive the one or more samples from the buffer.

3 . The receiver of claim 1 wherein the timing control circuit generates the timing error based at least in part on computations relating to a cyclic prefix of a first one of the one or more orthogonal frequency division multiplexing symbols.

4 . The receiver of claim 3 wherein the timing control circuit generates the timing error based at least in part on a difference between a first correlation sum for a first portion of a cyclic prefix of a first one of the one or more orthogonal frequency division multiplexing symbols and a second correlation sum for a second portion of the cyclic prefix.

5 . The receiver of claim 4 wherein the timing control circuit is configured to control the sample rate converter to adjust the sample rate according to a difference between the first correlation sum and the second correlation sum of the one or more orthogonal frequency division multiplexing symbols received via a multi-path channel.

6 . The receiver of claim 4 wherein the timing control circuit is configured to control the sample rate converter to adjust the sample rate until the first correlation sum is at least substantially equal to the second correlation sum.

7 . The receiver of claim 4 wherein the timing control circuit includes a cyclic prefix correlator configured to calculate first cyclic prefix correlations for the first portion of the cyclic prefix and second cyclic prefix correlations for the second portion of the cyclic prefix, and to calculate first guard band correlations for one or more first guard band samples adjacent the first portion of the cyclic prefix and second guard band correlations for one or more second guard band samples adjacent the second portion of the cyclic prefix

8 . The receiver of claim 7 further comprising a summer configured to calculate the first correlation sum based on the first cyclic prefix correlations and the first guard band correlations, and to calculate the second correlation sum based on the second cyclic prefix correlations and the second guard band correlations.

9 . The receiver of claim 4 wherein the timing control circuit is configured to determine a timing error based on a comparison of the first correlation sum and the second correlation sum.

10 . The receiver of claim 4 wherein the timing control circuit is further configured to maintain a first count and a second count based on the timing error for a plurality of comparisons of the first correlation sum and the second correlation sum.

11 . A wireless communication device comprising:
an antenna; transceiver circuitry in communication with the antenna and configured to configured to receive one or more orthogonal divisional multiplexing signals from the antenna, the transceiver circuitry including: a sample rate converter configured to output one or more samples of one or more orthogonal frequency division multiplexing symbols; a fast Fourier transform engine configured to receive the one or more samples and convert each of the one or more samples into a plurality of frequency domain sub-carriers; and a timing control circuit configured to generate a timing error, and control the sample rate converter to adjust a sample rate of the one or more orthogonal frequency division multiplexing symbols based at least in part on the timing error.

12 . The wireless communication device of claim 11 wherein the transceiver circuitry includes a buffer configured to store the one or more samples of one or more orthogonal frequency division multiplexing symbols, the fast Fourier transform engine configured to receive the one or more samples from the buffer.

13 . The wireless communication device of claim 11 wherein the timing control circuit generates the timing error based at least in part on computations relating to a cyclic prefix of a first one of the one or more orthogonal frequency division multiplexing symbols.

14 . The wireless communication device of claim 13 wherein the timing control circuit generates the timing error based at least in part on a difference between a first correlation sum for a first portion of a cyclic prefix of a first one of the one or more orthogonal frequency division multiplexing symbols and a second correlation sum for a second portion of the cyclic prefix.

15 . The wireless communication device of claim 14 wherein the timing control circuit is configured to control the sample rate converter to adjust the sample rate according to a difference between the first correlation sum and the second correlation sum of the one or more orthogonal frequency division multiplexing symbols received via a multi-path channel.

16 . The wireless communication device of claim 14 wherein the timing control circuit is configured to control the sample rate converter to adjust the sample rate until the first correlation sum is at least substantially equal to the second correlation sum.

17 . The wireless communication device of claim 14 wherein the timing control circuit includes a cyclic prefix correlator configured to calculate first cyclic prefix correlations for the first portion of the cyclic prefix and second cyclic prefix correlations for the second portion of the cyclic prefix, and to calculate first guard band correlations for one or more first guard band samples adjacent the first portion of the cyclic prefix and second guard band correlations for one or more second guard band samples adjacent the second portion of the cyclic prefix

18 . The wireless communication device of claim 17 further comprising a summer configured to calculate the first correlation sum based on the first cyclic prefix correlations and the first guard band correlations, and to calculate the second correlation sum based on the second cyclic prefix correlations and the second guard band correlations.

19 . The wireless communication device of claim 14 wherein the timing control circuit is configured to determine a timing error based on a comparison of the first correlation sum and the second correlation sum.

20 . A method of receiving orthogonal division multiplexing symbols, the method comprising:
receiving, in a receiver, a radio frequency signal; processing, in the receiver, the radio frequency signal to obtain a plurality of orthogonal division multiplexing symbols, each of the plurality of orthogonal division multiplexing symbols including cyclic prefix samples and information samples; determining a timing error based on computations relating to the cyclic prefix samples; controlling a sample rate converter to adjust a sample rate of the plurality of orthogonal division multiplexing symbols based at least in part on the timing error.

Assignees

• Skyworks Solutions Inc

Inventors

• Kleinerman Alexander
• Blasie Connor William
• Wallace Bradley Arthur

Classifications

• H04L27/2662 Primary

  Symbol synchronisation · CPC title

• H04L27/2678 Primary

  using cyclostationarities, e.g. cyclic prefix or postfix · CPC title

• H04L27/2607

  Cyclic extensions · CPC title

• H04L27/2663

  Coarse synchronisation, e.g. by correlation · CPC title

• H04L27/2671

  Time domain · CPC title