Oversampled Phase Lock Loop in a Read Channel

Patent metadata

Field	Value
Publication number	US-2024120925-A1
Application number	US-202217958877-A
Country	US
Kind code	A1
Filing date	Oct 3, 2022
Priority date	Oct 3, 2022
Publication date	Apr 11, 2024
Grant date	—

Abstract

Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.

First claim

What is claimed is:

1 . A channel circuit, comprising:
a phase lock loop configured to:
receive a digital data signal representing a series of data bits at a baud rate from an analog read signal, wherein the digital data signal includes oversampled digital signal values at a sample rate that is a multiple of the baud rate;
determine a bit data pattern from the oversampled digital signal values of the digital data signal;
determine, based on the bit data pattern and a bit response signal, an ideal signal;
determine, based on a comparison of the bit data pattern and the ideal signal, a phase gradient; and
feedback, based on the phase gradient, a phase correction for a next iteration of the phase lock loop.

2 . The channel circuit of claim 1 , further comprising:
an analog-to-digital converter configured to:
generate, based on the sample rate, the oversampled digital signal values from the analog read signal;
receive, from the phase lock loop, the phase correction; and
correct a phase of a next set of oversampled digital signal values.

3 . The channel circuit of claim 1 , further comprising:
a down sample circuit configured to:
receive the oversampled digital signal values;
down sample the oversampled digital signal values to a baud rate digital signal; and
send the baud rate digital signal for data processing.

4 . The channel circuit of claim 1 , further comprising:
a signal interpolator configured to:
interpolate a set of oversampled digital signal values to approximate digital signal values between oversampled digital signal values in the set of oversampled digital signal values; and
determine a corresponding set of baud rate digital signal values based on the phase gradient corresponding to the ideal signal.

5 . The channel circuit of claim 4 , wherein:
the phase lock loop is further configured to use a first time constant for feedback of the phase correction for the next iteration of the phase lock loop; the signal interpolator is further configured to use a second time constant for determining the corresponding set of baud rate digital signal values; and the first time constant is larger than the second time constant.

6 . The channel circuit of claim 1 , wherein the phase lock loop comprises an iterative detector configured to:
determine the bit data pattern from the oversampled digital signal values; determine the bit response signal from the oversampled digital signal values; and determine, based on the bit data pattern and a bit response signal, the ideal signal.

7 . The channel circuit of claim 6 , wherein the phase lock loop further comprises a gradient engine configured to:
compare the bit data pattern and the ideal signal; and determine, based on the comparison of the bit data pattern and the ideal signal, the phase gradient.

8 . The channel circuit of claim 7 , wherein the sample rate is at least double the baud rate of the channel circuit.

9 . A data storage device comprising the channel circuit of claim 1 and further comprising:
a non-volatile storage medium configured to store data; and
at least one read element configured to generate the analog read signal from the non-volatile storage medium.

10 . The data storage device of claim 9 , wherein:
the non-volatile storage medium comprises magnetic tape comprised of a plurality of data tracks; the at least one read element includes a plurality of read elements corresponding to the plurality of data tracks; and the phase lock loop is further configured to correct phase across the plurality of data tracks based on oversampled digital signal values from a plurality of analog read signals corresponding to the plurality of data tracks.

11 . A method comprising:
receiving, in a phase lock loop, a digital data signal representing a series of data bits at a baud rate from an analog read signal, wherein the digital data signal includes oversampled digital signal values at a sample rate that is a multiple of the baud rate; determining a bit data pattern from the oversampled digital signal values of the digital data signal; determining, based on the bit data pattern and a bit response signal, an ideal signal; determining, based on a comparison of the bit data pattern and the ideal signal, a phase gradient; and feeding back, based on the phase gradient, a phase correction for a next iteration of the phase lock loop.

12 . The method of claim 11 , further comprising:
generating, by an analog-to-digital converter and based on the sample rate, the oversampled digital signal values from the analog read signal; receiving, by the analog-to-digital converter and from the phase lock loop, the phase correction; and correcting a phase of a next set of oversampled digital signal values.

13 . The method of claim 11 , further comprising:
down sampling the oversampled digital signal values to a baud rate digital signal; and sending the baud rate digital signal for data processing.

14 . The method of claim 11 , further comprising:
interpolating a set of oversampled digital signal values to approximate digital signal values between oversampled digital signal values in the set of oversampled digital signal values; and determining a corresponding set of baud rate digital signal values based on the phase gradient corresponding to the ideal signal.

15 . The method of claim 14 , wherein:
the phase lock loop uses a first time constant for feedback of the phase correction for the next iteration of the phase lock loop; a signal interpolator uses a second time constant for determining the corresponding set of baud rate digital signal values; and the first time constant is larger than the second time constant.

16 . The method of claim 11 , further comprising:
determining the bit response signal from the oversampled digital signal values; and comparing the bit data pattern and the ideal signal.

17 . The method of claim 11 , wherein the sample rate is at least double the baud rate.

18 . The method of claim 11 , further comprising:
reading a plurality of analog read signals from a plurality of data tracks on a magnetic tape; generating a plurality of digital data signals comprising a plurality of oversampled digital signal values from the plurality of analog read signals; and correcting phase across the plurality of data tracks based on the plurality of oversampled digital signal values.

19 . A system comprising:
means for receiving a digital data signal representing a series of data bits at a baud rate from an analog read signal, wherein the digital data signal includes oversampled digital signal values at a sample rate that is a multiple of the baud rate; means for determining a bit data pattern from the oversampled digital signal values of the digital data signal; means for determining, based on the bit data pattern and a bit response signal, an ideal signal; means for determining, based on a comparison of the bit data pattern and the ideal signal, a phase gradient; and means for feeding back, based on the phase gradient, a phase correction for a next iteration of the phase lock loop.

Assignees

• Western Digital Tech Inc

Inventors

• Oboukhov Iouri
• Burton Derrick E
• Galbraith Richard

Classifications

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0998

  using phase interpolation · CPC title