Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2024114683-A1
Application number	US-202217958922-A
Country	US
Kind code	A1
Filing date	Oct 3, 2022
Priority date	Oct 3, 2022
Publication date	Apr 4, 2024
Grant date	—

Abstract

A method of manufacturing a memory device includes providing a substrate and sequentially forming a stack layer and a hard mask layer on the substrate. The method includes forming a first patterned mandrel and a plurality of second patterned mandrels on the hard mask layer, wherein the first patterned mandrel is adjacent to and spaced apart from an end of the second patterned mandrels in the first direction. The method further includes using the first patterned mandrel and the second patterned mandrels as masks, patterning the hard mask layer and the stack layer sequentially to form a dummy structure and a plurality of word lines separated from each other on the substrate. A portion of the stack layer corresponding to the first mandrel is formed into the dummy structure, and a portion of the stack layer corresponding to the second patterned mandrels is formed into the word lines.

First claim

What is claimed is:

1 . A method of manufacturing a memory device, comprising:
providing a substrate; sequentially forming a stack layer and a hard mask layer on the substrate; forming a first patterned mandrel and a plurality of second patterned mandrels on the hard mask layer, wherein the first patterned mandrel is adjacent to and spaced apart from an end of the second patterned mandrels in a first direction; and using the first patterned mandrel and the second patterned mandrels as masks, patterning the hard mask layer and the stack layer sequentially to form a dummy structure and a plurality of word lines separated from each other on the substrate, wherein a portion of the stack layer corresponding to the first mandrel is formed into the dummy structure, and a portion of the stack layer corresponding to the second patterned mandrels is formed into the word lines.

2 . The method as claimed in claim 1 , wherein the first patterned mandrel extends in a second direction and comprises a plurality of closed openings, and the second patterned mandrels extend in the first direction and are arranged in the second direction, wherein the first direction intersects the second direction.

3 . The method as claimed in claim 2 , wherein a ratio of a width of each of the closed openings in the second direction to a pitch of the second patterned mandrels is about 1:1, and a ratio of the width of each of the closed openings in the second direction to a width of each of the second patterned mandrels in the second direction is about 3:1.

4 . The method as claimed in claim 1 , wherein sequentially patterning the hard mask layer and the stack layer to form the word lines comprises:
forming a plurality of spacers on opposite sidewalls of the second patterned mandrels; transferring a pattern of the second patterned mandrels and a pattern of the spacers to the hard mask layer and removing the second patterned mandrels, while leaving the spacers on the hard mask layer; and sequentially transferring the pattern of the spacers to the hard mask layer and the stack layer to form the word lines on the substrate.

5 . The method as claimed in claim 4 , wherein forming the spacers further comprises: forming a connecting portion of the spacers at the end of the second patterned mandrels, and after removing the second patterned mandrels, the method further comprises:
forming a first patterned photoresist covering a portion of the spacers on the opposite sidewalls of the second patterned mandrels, while exposing the connecting portion of the spacers at the end of the second patterned mandrels; and removing the connecting portion of the spacers at the end of the second patterned mandrels, so that remaining portions of the spacers are not connected to each other.

6 . The method as claimed in claim 5 , wherein the remaining portions of the spacers are arranged in a second direction, the first direction intersects the second direction, and a width of each of the spacers in the second direction is equal to a spacing of the spacers in the second direction.

7 . The method as claimed in claim 4 , wherein sequentially transferring the pattern of the spacers to the hard mask layer and the stack layer comprises:
forming a second patterned photoresist covering a portion of the hard mask layer corresponding to the first patterned mandrel while exposing the spacers; transferring the pattern of the spacers to the hard mask layer underlying the spacers; removing the second patterned photoresist and the spacers; and transferring a pattern of the hard mask layer to the stack layer to form the word lines on the substrate.

8 . The method as claimed in claim 1 , wherein before forming the hard mask layer on the stack layer, the method further comprises:
forming a sacrificial layer on the stack layer, the sacrificial layer protects the stack layer from etching during the patterning of the hard mask layer.

9 . The method as claimed in claim 8 , wherein the hard mask layer comprises polysilicon, and the sacrificial layer comprises silicon oxide.

10 . The method as claimed in claim 1 , wherein the dummy structure is rail-shaped and is a bulk body extending in a second direction with a plurality of closed openings arranged in the second direction, wherein the first direction intersects the second direction.

11 . The method as claimed in claim 10 , wherein a spacing of the closed openings in the second direction is greater than a width of each of the word lines.

12 . The method as claimed in claim 1 , wherein a spacing between the first patterned mandrel and the second patterned mandrels is about 50 nm to about 110 nm.

13 . A memory device, comprising:
a substrate; a plurality of word lines disposed on the substrate, wherein the word lines extend in a first direction and are arranged in a second direction, and the first direction intersects the second direction; and a dummy structure disposed on the substrate, wherein the dummy structure is adjacent to and spaced apart from an end of the word lines in the first direction, wherein the dummy structure is a bulk body extending in the second direction with a plurality of closed openings arranged in the second direction.

14 . The memory device as claimed in claim 13 , wherein the dummy structure is rail-shaped.

15 . The memory device as claimed in claim 13 , further comprising:
two select gates respectively disposed on opposite sides of the word lines in the second direction, wherein the two select gates extend in the first direction, and the dummy structure is between the two select gates in the second direction.

16 . The memory device as claimed in claim 13 , further comprising:
a plurality of landing pads that extend in the second direction, respectively connected with another plurality of word lines, wherein the dummy structure is between the landing pads and the word lines.

17 . The memory device as claimed in claim 13 , wherein a ratio of a width of each of the closed openings in the second direction to a pitch of the word lines is about 1:1.

18 . The memory device as claimed in claim 13 , wherein a spacing between the dummy structure and the word lines is about 50 nm to about 110 nm.

19 . The memory device as claimed in claim 13 , wherein a spacing of each of the closed openings in the second direction is greater than a width of each of the word lines.

20 . The memory device as claimed in claim 13 , wherein a ratio of a width of each of the closed openings in the second direction to a pitch of the word lines is about 2:1.

Assignees

• Winbond Electronics Corp

Inventors

• Lin Tsung-Wei
• Wu Kun-Che
• Liao Chun-Yen
• Wu Chun-Sheng

Classifications

• H01L27/11524 Primary

  Electricity · mapped topic

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B12/488 Primary

  Word lines · CPC title