Hybrid performance monitoring unit (pmu) enumeration

Patent metadata

Field	Value
Publication number	US-2024111654-A1
Application number	US-202318374296-A
Country	US
Kind code	A1
Filing date	Sep 28, 2023
Priority date	Sep 29, 2022
Publication date	Apr 4, 2024
Grant date	—

Abstract

Detailed herein are examples of hybrid (heterogenous) performance monitoring unit enumeration. In some examples, a processor supports an instruction that enumerates performance monitoring unit enumeration. For example, the processor comprises decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.

First claim

What is claimed is:

1 . An apparatus comprising:
decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.

2 . The apparatus of claim 1 , wherein the performance monitoring unit's capabilities are enumerated using a leaf at EAX=23H.

3 . The apparatus of claim 1 , wherein the heterogenous performance monitoring unit capabilities include an indication of valid sub-leafs.

4 . The apparatus of claim 1 , wherein the heterogenous performance monitoring unit capabilities include an indication of supported general-purpose counters.

5 . The apparatus of claim 1 , wherein the heterogenous performance monitoring unit capabilities include an indication of supported fixed-function counters.

6 . The apparatus of claim 1 , wherein the heterogenous performance monitoring unit capabilities include an indication of supported performance monitor events.

7 . The apparatus of claim 1 , wherein the opcode is 0F A2.

8 . A method comprising:
decoding an instance of a single instruction, the single instruction to include a field for an opcode; and executing the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.

9 . The method of claim 8 , wherein the heterogenous performance monitoring unit capabilities are enumerated using a leaf at EAX=23H.

10 . The method of claim 8 , wherein the heterogenous performance monitoring unit capabilities enumerated include an indication of valid sub-leafs.

11 . The method of claim 8 , wherein the heterogenous performance monitoring unit capabilities enumerated include an indication of supported general-purpose counters.

12 . The method of claim 8 , wherein the heterogenous performance monitoring unit capabilities enumerated include an indication of supported fixed-function counters.

13 . The method of claim 8 , wherein the heterogenous performance monitoring unit capabilities enumerated include an indication of supported performance monitor events.

14 . The method of claim 8 , wherein the opcode is 0F A2.

15 . A system comprising method comprising:
memory to store an instance of a single instruction; a processor core including:
decoder circuitry to decode the instance of the single instruction, the single instruction to include a field for an opcode; and
execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.

16 . The system of claim 15 , wherein the heterogenous performance monitoring unit capabilities are enumerated using a leaf at EAX=23H.

17 . The system of claim 15 , wherein the heterogenous performance monitoring unit capabilities enumerated include an indication of valid sub-leafs.

18 . The system of claim 15 , wherein the heterogenous performance monitoring unit capabilities enumerated include an indication of supported general-purpose counters.

19 . The system of claim 15 , wherein the heterogenous performance monitoring unit capabilities enumerated include an indication of supported fixed-function counters.

20 . The system of claim 15 , wherein the heterogenous performance monitoring unit capabilities enumerated include an indication of supported performance monitor events.

Assignees

• Intel Corp

Inventors

• Rivas Toledano Raoul
• Kapaley Udayan
• Yasin Ahmad
• Gopalakrishnan Karthik
• Torrant Marc

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30076 Primary

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F11/3466 Primary

  Performance evaluation by tracing or monitoring · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F11/3409

  for performance assessment · CPC title