Image sensor and image processing device including the same

Patent metadata

Field	Value
Publication number	US-2024107195-A1
Application number	US-202318240483-A
Country	US
Kind code	A1
Filing date	Aug 31, 2023
Priority date	Sep 23, 2022
Publication date	Mar 28, 2024
Grant date	—

Abstract

An image sensor comprising a pixel array in which a plurality of pixels are arranged and a row driver . Each of the pixel includes a photodiode, a transfer transistor for transferring photocharges of the photodiode to a floating diffusion node (FD), a conversion gain control transistor, a first source follower for amplifying and outputting the voltage of the FD to a first node, a precharge selection transistor connected between the first node and a second node, a first capacitor, a first sampling transistor connected between the second node and the first capacitor, a second capacitor, a second sampling transistor connected between the second node and the second capacitor, a second source follower for amplifying a voltage of the second node, a first selection transistor connected between the second source follower and a column line, and a second selection transistor connected between the first node and the column line.

First claim

What is claimed is:

1 . An image sensor comprising:
a pixel array in which a plurality of pixels are arranged; and a row driver configured to transmit control signals to the pixel array, wherein the plurality of pixels each include
a first photodiode,
a first transfer transistor configured to transfer photocharges generated by the first photodiode to a floating diffusion node,
a conversion gain control transistor connected to the floating diffusion node and configured to adjust a rate at which the photocharges are converted into a voltage of the floating diffusion node,
a first source follower configured to amplify the voltage of the floating diffusion node and output the amplified voltage to a first node,
a precharge selection transistor having one end connected to the first node and another end connected to a second node,
a first capacitor configured to sample a reset voltage corresponding to a voltage level of the floating diffusion node that is reset,
a first sampling transistor having one end connected to the second node and another end connected to the first capacitor,
a second capacitor configured to sample a first image voltage corresponding to the voltage level of the floating diffusion node according to the photocharges generated by the first photodiode,
a second sampling transistor having one end connected to the second node and another end connected to the second capacitor,
a second source follower configured to amplify a voltage of the second node and output the amplified voltage,
a first selection transistor connected between an output terminal of the second source follower and a column line, and
a second selection transistor connected between the first node and the column line.

2 . The image sensor of claim 1 , wherein, the first selection transistor is configured to, when the pixel array operates in a first shutter mode, output an output voltage of the second source follower to the column line as a pixel signal, and
the second selection transistor is configured to, when the pixel array operates in a second shutter mode, output a voltage of the first node to the column line as the pixel signal.

3 . The image sensor of claim 2 , wherein, when the pixel array operates in the first shutter mode, the second selection transistor is turned off, and
when the pixel array operates in the second shutter mode, the precharge selection transistor, the first sampling transistor, the second sampling transistor, and the first selection transistor are turned off.

4 . The image sensor of claim 2 , wherein, when the pixel array operates in the first shutter mode, the reset voltage is sampled in the first capacitor during a first period in the plurality of pixels and the first image voltage is sampled in the second capacitor.

5 . The image sensor of claim 4 , wherein, the plurality of pixels are configured to, during a second period subsequent to the first period, sequentially output the reset voltage sampled in the first capacitor and the first image voltage sampled in the second capacitor to the column line as the pixel signal in units of rows.

6 . The image sensor of claim 5 , wherein the precharge selection transistor is turned on during the second period so that the second node is precharged based on the reset voltage,
after the second node is precharged, the first sampling transistor is turned on so that the reset voltage sampled in the first capacitor is output to the column line as the pixel signal, after the reset voltage is output to the column line as the pixel signal, the precharge selection transistor is turned on so that the second node is precharged again based on the reset voltage, and after the second node is precharged again, the second sampling transistor is turned on so that the first image voltage sampled in the second capacitor is output to the column line as the pixel signal.

7 . The image sensor of claim 5 , wherein, the plurality of pixels are configured to, when the pixel array operates in the first shutter mode, sequentially output the pixel signal to the column line in units of rows,
the plurality of pixels are configured to, after the plurality of pixels output the reset voltage output from the first source follower to the column line as the pixel signal, output the first image voltage to the column line as the pixel signal, and the second selection transistor is further configured to, during a second period subsequent to the first period, output the first image voltage of the floating diffusion node, which is output from the second source follower, to the column line as the pixel signal.

8 . The image sensor of claim 2 , wherein the plurality of pixels each further comprise:
a second photodiode; a second transfer transistor configured to transfer photocharges generated by the second photodiode to the floating diffusion node; a third capacitor configured to sample a second image voltage corresponding to a voltage level of the floating diffusion node corresponding to photocharges generated by the first photodiode and the second photodiode; and a third sampling transistor having one end connected to the second node and another end connected to the third capacitor.

9 . The image sensor of claim 8 , wherein, when the pixel array operates in the first shutter mode, the reset voltage is sampled in the first capacitor during a first period in the plurality of pixels, the first image voltage is sampled in the second capacitor, and the second image voltage is sampled in the third capacitor.

10 . The image sensor of claim 9 , wherein the plurality of pixels are configured to, during a second period subsequent to the first period, sequentially output the reset voltage sampled in the first capacitor, the first image voltage sampled in the second capacitor, and the second image voltage sampled in the third capacitor to the column line as the pixel signal in units of rows.

11 . An image sensor comprising:
a pixel array in which a plurality of pixels are arranged; and a row driver configured to transmit control signals to the pixel array, wherein the plurality of pixels each include
a plurality of sub-pixels each comprising a first photodiode and a second photodiode,
a conversion gain control transistor connected to a floating diffusion node at which photocharges transferred from at least one of the plurality of sub-pixels are integrated, and configured to adjust a rate at which the photocharges are converted into a voltage of the floating diffusion node,
a first source follower configured to amplify the voltage of the floating diffusion node and output the amplified voltage to a first node,
a precharge selection transistor having one end connected to the first node and another end connected to a second node,
a first sampling transistor having one end connected to the second node,
a first capacitor having one end connected to another end of the first sampling transistor and another end to which a power supply voltage is applied,
a second sampling transistor having one end connected to the second node,
a second capacitor having one end connected to another end of the second sampling transistor and another end to which the power supply voltage is applied,
a third sampling transistor having one end connected to the second node,
a third capacitor having one end connected to another end of the third sampling transistor and another end to which the power supply voltage is applied,
a second source follower configured to amplify a voltage of the second node and output the amplified voltage,
a first selection transistor connected between an output terminal of the second source follower and a column line, and
a second sel

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shim Heesung
• Kim Seungsik
• Lee Jaekyu
• Lim Seunghyun
• Jun Sungjae

Classifications

• H04N25/771 Primary

  comprising storage means other than floating diffusion · CPC title

• H04N23/667

  Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes · CPC title

• H04N25/531 Primary

  by controlling rolling shutters in CMOS SSIS · CPC title

• H04N25/532

  by controlling global shutters in CMOS SSIS · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title