Measurement system, related integrated circuit and method

Patent metadata

Field	Value
Publication number	US-2024106401-A1
Application number	US-202318369583-A
Country	US
Kind code	A1
Filing date	Sep 18, 2023
Priority date	Sep 19, 2022
Publication date	Mar 28, 2024
Grant date	—

Abstract

A measurement system, featuring first and second capacitances, and switching, control, and measurement circuits, charges/discharges the capacitances during normal operation. The switching and control circuits periodically connect a first terminal of the first capacitance to a first voltage and a reference voltage, and a first terminal of the second capacitance to a second voltage and the reference voltage. The second terminal of the first capacitance and the second terminal of the second capacitance are connected to the input terminals of the differential integrator, the charge difference between the capacitances being transferred to the differential integrator. A comparator triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator. Two decoupling capacitances are connected between the input of the comparator and the output of the differential integrator, and two reset phases are used to store various disturbances to these decoupling capacitances, improving precision.

First claim

1 . A measurement system, comprising:
a first capacitance and a second capacitance; a switching circuit configured to receive a first control signal and a second control signal and:
in response to said first control signal being asserted, connect a first terminal of said first capacitance to a first voltage and a first terminal of said second capacitance to a second voltage; and
in response to said second control signal being asserted, connect said first terminal of said first capacitance and said first terminal of said second capacitance to a reference voltage;
a control circuit configured to generate said first control signal and said second control signal according to switching cycles, wherein said control circuit is configured to repeat, during each switching cycle:
for a first interval, de-assert said first control signal and said second control signal,
for a second interval, de-assert said first control signal and assert said second control signal,
for a third interval, de-assert said first control signal and said second control signal, and
for a fourth interval, assert said first control signal and de-assert said second control signal;
a measurement circuit comprising:
a differential integrator comprising:
a differential operational amplifier having an inverting input connected to a second terminal of said first capacitance and a non-inverting input connected to a second terminal of said second capacitance;
a first integration capacitance having a first terminal connected to said inverting input of said differential operational amplifier and a second terminal connected via a first electronic switch to a positive output terminal of said differential operational amplifier;
a first output node of said differential integrator connected to said second terminal of said first integration capacitance;
a second integration capacitance having a first terminal connected to said non-inverting input of said differential operational amplifier and a second terminal connected via a second electronic switch to a negative output terminal of said differential operational amplifier;
a second output node of said differential integrator connected to said second terminal of said second integration capacitance;
a third electronic switch connected between said inverting input of said differential operational amplifier and said positive output terminal of said differential operational amplifier; and
a fourth electronic switch connected between said non-inverting input of said differential operational amplifier and said negative output terminal of said differential operational amplifier; and

a comparator with hysteresis configured, in response to a voltage applied to a negative input terminal of said comparator exceeding a voltage applied to a positive input terminal of said comparator plus a hysteresis threshold, to set a first output terminal of said comparator to high and a second output terminal of said comparator to low, wherein said comparator comprises:
a fifth electronic switch connected between said negative input terminal of said comparator and said second output terminal of said comparator;
a sixth electronic switch connected between said positive input terminal of said comparator and said first output terminal of said comparator;
a first decoupling capacitance connected between the negative input terminal of said comparator and said first output node of said differential integrator; and
a second decoupling capacitance connected between the positive input terminal of said comparator and said second output node of said differential integrator;

the control circuit further configured to:
during a normal operation phase:
close said first electronic switch and said second electronic switch by asserting said second control signal, and open said first electronic switch and said second electronic switch by de-asserting said second control signal;
close said third electronic switch and said fourth electronic switch by asserting said first control signal, and open said third electronic switch and said fourth electronic switch by de-asserting said first control signal;
open said fifth electronic switch and said sixth electronic switch; and
monitor a reset request signal indicating a reset request and start a reset phase in response to determining that said reset request signal indicates a reset request; and

during said reset phase:
for a first reset interval, close said first electronic switch, second electronic switch, third electronic switch, fourth electronic switch, fifth electronic switch and sixth electronic switch; and
for a second reset interval, open said third electronic switch and said fourth electronic switch and maintain said first electronic switch, second electronic switch, fifth electronic switch, and sixth electronic switch as being closed, and then start said normal operation phase again.

2 . The measurement system according to claim 1 ,
wherein said differential integrator is configured to receive a first reset signal, wherein said third electronic switch and said fourth electronic switch are configured to be closed in response to said first control signal being asserted or said first reset signal being asserted; wherein said comparator is configured to receive a second reset signal, wherein said fifth electronic switch and said sixth electronic switch are configured to be closed in response to said second reset signal being asserted; and wherein control circuitry is configured, while said second control signal is asserted:
for said first reset interval, to assert said first reset signal and said second reset signal, and
for said second reset interval, to de-assert said first reset signal and assert said second reset signal.

3 . The measurement system according to claim 2 , further comprising a delay circuit configured to generate said second reset signal by delaying said first reset signal.

4 . The measurement system according to claim 1 , wherein said measurement circuit is configured to assert said reset request signal after a given maximum number of said switching cycles.

5 . The measurement system according to claim 1 , wherein said measurement circuit is configured to assert said reset request signal in response to determining that said first output terminal of said comparator is set to high; or wherein said measurement circuit is configured to assert said reset request signal in response to determining that said second output terminal of said comparator is set to low.

6 . The measurement system according to claim 1 , further comprising: a processing circuit configured to monitor a signal at said first output terminal of said comparator; or a processing circuit configured to monitor a signal at said second output terminal of said comparator.

7 . The measurement system according to claim 1 , wherein said first capacitance corresponds to a sense capacitance and said second capacitance corresponds to a reference capacitance, wherein said first voltage and said second voltage have a common voltage, and wherein the voltage between the first output node and second output node of said differential integrator is indicative of a difference between capacitance values of said sense capacitance and said reference capacitance.

8 . The measurement system according to claim 7 , further comprising a voltage generator configured to generate said common voltage.

9 . The measurement system according to claim 8 ,
further comprising a plurality of sense capacitances, wherein said switching circuit comprises for each sense capacitance a respective half-bridge, wherein each half-bridge comprises a high-side electronic switch connected between said common voltage and a first terminal of the respective

Assignees

• St Microelectronics Srl

Inventors

• Nicollini Germano
• Vaiana Michele

Classifications

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F1/26

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03F3/45273

  Mirror types · CPC title

• H03F2200/261

  Amplifier which being suitable for instrumentation applications · CPC title

• G01R27/2605 Primary

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title