Semiconductor device and manufacturing method of a semiconductor device

Patent metadata

Field	Value
Publication number	US-2024074187-A1
Application number	US-202318092790-A
Country	US
Kind code	A1
Filing date	Jan 3, 2023
Priority date	Aug 26, 2022
Publication date	Feb 29, 2024
Grant date	—

Abstract

A semiconductor device includes a gate structure including word lines and select lines, the gate structure including a first pad stepped structure for exposing each of the select lines and a common pad structure for exposing the select lines. The semiconductor device also includes first contact plugs connected to the select lines through the first pad stepped structure, respectively. The semiconductor device further includes one or more common contact plugs connected in common to the select lines through the common pad structure.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a gate structure including word lines and select lines, the gate structure including a first pad stepped structure for exposing each of the select lines and a common pad structure for exposing the select lines; contact plugs connected to the select lines through the first pad stepped structure, respectively; and one or more common contact plugs connected in common to the select lines through the common pad structure.

2 . The semiconductor device of claim 1 , wherein the first pad stepped structure has a structure in which first sidewalls of the select lines are spaced apart from each other.

3 . The semiconductor device of claim 1 , wherein the contact plugs are connected to upper surfaces of the select lines exposed through the first pad stepped structure, respectively.

4 . The semiconductor device of claim 1 , wherein the common pad structure has a structure in which second sidewalls of the select lines are aligned with each other.

5 . The semiconductor device of claim 1 , wherein the common contact plugs are connected in common to second sidewalls of the select lines.

6 . The semiconductor device of claim 1 , wherein the common pad structure has a structure in which an upper surface of a lowermost select line among the select lines is exposed, and second sidewalls of remaining select lines are aligned with each other.

7 . The semiconductor device of claim 6 , wherein the common contact plugs are connected in common to the upper surface of the lowermost selection line and the second sidewalls of the remaining selection lines.

8 . The semiconductor device of claim 1 , wherein the common contact plug has a greater width than widths of the contact plugs.

9 . The semiconductor device of claim 1 , wherein the contact plugs are arranged in a first direction, and the common contact plugs are arranged in a second direction intersecting the first direction.

10 . The semiconductor device of claim 1 , wherein the gate structure includes a second pad stepped structure,
wherein the second pad stepped structure is located to face the common pad structure with the first pad stepped structure interposed between the second pad stepped structure and the common pad structure, and wherein the second pad stepped structure exposes the word lines, respectively.

11 . The semiconductor device of claim 10 , wherein the gate structure includes a dummy stepped structure,
wherein the dummy stepped structure is connected to the common pad structure, and wherein the dummy stepped structure exposes the word lines, respectively.

12 . The semiconductor device of claim 1 , further comprising:
channel structures located between the first pad stepped structure and the common pad structure, the channel structures passing through the gate structure.

13 . The semiconductor device of claim 12 , wherein select transistors are located in a region where the channel structures and the selection lines intersect with each other.

14 . The semiconductor device of claim 13 , wherein a bias is applied in common to the selection lines through the contact plugs and the common contact plug when the select transistors are operated.

15 . A semiconductor device comprising:
a gate structure including a first gate line and a second gate line; a first contact plug connected to the first gate line; a second contact plug connected to the second gate line; and a common contact plug connected in common to the first gate line and the second gate line, wherein a bias is applied in common to the first gate line and the second gate line through the first contact plug, the second contact plug, and the common contact plug when the first gate line and the second gate line are operated.

16 . The semiconductor device of claim 15 , wherein the gate structure comprises:
a pad stepped structure exposing the first gate line and the second gate line, respectively; and a common pad structure exposing the first gate line and the second gate line.

17 . The semiconductor device of claim 15 , further comprising:
a channel structure located between the first contact plug and the common contact plug, the channel structure passing through the gate structure.

18 . The semiconductor device of claim 17 , further comprising:
a first transistor located at an intersection region of the channel structure and the first gate line; and a second transistor located at an intersection region of the channel structure and the second gate line.

19 . The semiconductor device of claim 18 , wherein the first transistor and the second transistor are commonly driven by the bias.

20 . The semiconductor device of claim 15 , wherein the first gate line and the second gate line each are a drain select line or a source select line.

21 . A manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a stack including first material layers and second material layers that are alternately stacked; forming a first pad stepped structure exposing each of the first material layers in the stack; forming a common pad structure exposing the first material layers in the stack; forming contact plugs respectively connected to the first material layers through the first pad stepped structure; and forming one or more common contact plugs connected in common to the first material layers through the common pad structure.

22 . The manufacturing method of claim 21 , wherein forming the common pad structure comprises:
forming first stepped structures exposing the first material layers, respectively; forming second stepped structures by transferring some of the first stepped structures into the stack; and forming the common pad structure connected to one of the second stepped structures.

23 . The manufacturing method of claim 22 , wherein the second stepped structures each include a second pad stepped structure exposing each of the first material layers.

24 . The manufacturing method of claim 22 , further comprising:
forming third stepped structures by transferring at least one of the second stepped structures into the stack.

25 . The manufacturing method of claim 24 , wherein the third stepped structures each include a third pad stepped structure exposing each of the first material layers.

26 . The manufacturing method of claim 24 , wherein the third stepped structures each include a dummy stepped structure connected to the common pad structure.

27 . The manufacturing method of claim 21 , wherein the first pad stepped structure has a structure in which first sidewalls of the first material layers are spaced apart from each other.

28 . The manufacturing method of claim 27 , wherein the contact plugs are connected to upper surfaces of the first material layers exposed through the first pad stepped structure, respectively.

29 . The manufacturing method of claim 21 , wherein the common pad stepped structure has a structure in which second sidewalls of the first material layers are aligned with each other.

30 . The manufacturing method of claim 21 , further comprising:
forming a channel structure passing through the stack.

31 . The manufacturing method of claim 30 , wherein the first pad stepped structure and the common pad structure ar

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H01L23/5283

  Electricity · mapped topic

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title