Electronic devices comprising a stepped pillar region, and related methods

Patent metadata

Field	Value
Publication number	US-2024074184-A1
Application number	US-202217897976-A
Country	US
Kind code	A1
Filing date	Aug 29, 2022
Priority date	Aug 29, 2022
Publication date	Feb 29, 2024
Grant date	—

Abstract

An electronic device comprises memory pillars comprising a channel material. The memory pillars extend through both a cell region and a lateral contact region. A portion of the memory pillars in the lateral contact region comprise at least one first step and at least one second step. The electronic device comprises a source contact in direct contact with the channel material in the at least one second step of the portion of the memory pillars in the lateral contact region. Additional electronic devices and methods of forming an electronic device are also disclosed.

First claim

What is claimed is:

1 . An electronic device, comprising:
memory pillars comprising a channel material and extending through both a cell region and a lateral contact region, a portion of the memory pillars in the lateral contact region comprising:
at least one first step;
at least one second step; and
a source contact in direct contact with the channel material in the at least one second step of the portion of the memory pillars in the lateral contact region.

2 . The electronic device of claim 1 , wherein the lateral contact region comprises a stepped pillar region.

3 . The electronic device of claim 2 , wherein the at least one second step of the stepped pillar region in the lateral contact region exhibits a relatively smaller critical dimension than a critical dimension of the at least one first step of the stepped pillar region.

4 . The electronic device of claim 2 , wherein the at least one second step of the stepped pillar region in the lateral contact region exhibits a relatively smaller critical dimension than a critical dimension of the memory pillars of the cell region.

5 . The electronic device of claim 1 , wherein the channel material in the lateral contact region substantially fills the at least one second step of the memory pillars.

6 . The electronic device of claim 1 , further comprising a fill material adjacent to the channel material in the lateral contact region of the memory pillars.

7 . The electronic device of claim 6 , wherein a thickness of the fill material is less than a thickness of the channel material in the lateral contact region of the memory pillars.

8 . The electronic device of claim 6 , wherein a thickness of the fill material is greater than a thickness of the channel material in the lateral contact region of the memory pillars.

9 . The electronic device of claim 6 , wherein a thickness of the channel material in direct contact with the source contact is substantially equal to the thickness of the channel material in the cell region.

10 . The electronic device of claim 1 , wherein the at least one first step and the at least one second step exhibit sloped sidewalls.

11 . The electronic device of claim 1 , wherein a portion of the source contact proximal to the memory pillars is wider than a portion of the source contact distal to the memory pillars.

12 . The electronic device of claim 1 , wherein the channel material extends continuously along an entire height of the memory pillars.

13 . The electronic device of claim 1 , wherein a thickness of the channel material in direct contact with the source contact is greater than a thickness of the channel material in the cell region.

14 . An electronic device, comprising:
a bottom semiconductive material; a source contact adjacent to the bottom semiconductive material; a top semiconductive material adjacent to the source contact; tiers of alternating conductive materials and dielectric materials adjacent to the top semiconductive material; and pillars extending through the tiers, the top semiconductive material, and the source contact and into the bottom semiconductive material, the pillars comprising:
a channel material, wherein a thickness of the channel material laterally adjacent to the tiers is less than the thickness of the channel material laterally adjacent to the source contact.

15 . The electronic device of claim 14 , wherein a diameter of a portion of the pillars laterally adjacent to the top semiconductive material is greater than a diameter of a portion of the pillars laterally adjacent to the tiers of alternating conductive materials and dielectric materials.

16 . The electronic device of claim 14 , wherein a diameter of a portion of the pillars laterally adjacent to the source contact and the bottom semiconductive material is less than the diameter of a portion of the pillars laterally adjacent to the top semiconductive material.

17 . The electronic device of claim 14 , wherein the channel material comprises a polysilicon material, a III-V compound semiconductive material, a II-VI compound semiconductive material, an organic semiconductive material, GaAs, InP, GaP, GaN, an oxide semiconductive material, or a combination thereof.

18 . The electronic device of claim 14 , wherein the channel material in a cell region exhibits a different dopant concentration than the channel material in a lateral contact region.

19 . A method of forming an electronic device, the method comprising:
forming a bottom semiconductive material; forming a source contact sacrificial material adjacent to the bottom semiconductive material; forming a top semiconductive material adjacent to the source contact sacrificial material; removing a portion of the bottom semiconductive material, a portion of the source contact sacrificial material, and a portion of the top semiconductive material to form stepped openings; forming a sacrificial structure in the stepped openings; forming tiers adjacent to the top semiconductive material and the sacrificial structure; forming pillar openings through the tiers; removing the sacrificial structure from the stepped openings to form a stepped feature region; forming cell films in the pillar openings and the stepped feature region, the cell films comprising a channel material; removing a portion of the channel material in the pillar openings; selectively removing the source contact sacrificial material to form a source contact opening; and forming a source contact in the source contact opening extending laterally and contacting the channel material.

20 . The method of claim 19 , further comprising forming a fill material adjacent to the channel material in the stepped feature region.

21 . The method of claim 19 , wherein removing a portion of the bottom semiconductive material, a portion of the source contact sacrificial material, and a portion of the top semiconductive material to form stepped openings comprises etching a slot in the top semiconductive material, forming a liner adjacent to the slot, etching an additional slot through the liner and through the source contact sacrificial material and the bottom semiconductive material, and removing the remaining portion of the liner.

Assignees

• Micron Technology Inc

Inventors

• Higuchi Masaaki
• Fukuzumi Yoshiaki
• Ishigaki Hirokazu

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11519

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic