Semiconductor device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-2024071907-A1
Application number	US-202318197768-A
Country	US
Kind code	A1
Filing date	May 16, 2023
Priority date	Aug 24, 2022
Publication date	Feb 29, 2024
Grant date	—

Abstract

A semiconductor device includes first and second substrates connected to each other. The second substrate includes a plate layer having first and second faces. Gate electrode layers are disposed on the first face of the plate layer. Channel structures extend through the gate electrode layers. Word-line cutting structures extend through the gate electrode layers and are spaced apart from each other. Via structures are disposed on the second face of the plate layer. Via connecting structures are disposed on the top face of the via structures. A width of the bottom face of each of the via structures is greater than a width of the top face of each of the via structures. A width of the bottom face of each of the via connecting structures is less than a width of the top face of each of the via connecting structures.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first substrate structure including a first substrate, circuit elements disposed on the first substrate, and first bonding metal layers disposed on the circuit elements; and a second substrate structure disposed on the first substrate structure, wherein the second substrate structure is connected to the first substrate structure, wherein the second substrate structure includes: a plate layer including a conductive material, the plate layer having first and second faces opposite to each other; gate electrode layers disposed on the first face of the plate layer, the gate electrode layers are stacked on top of each other in a first direction perpendicular to the first face of the plate layer and are spaced apart from each other in the first direction; channel structures extending through the gate electrode layers in the first direction; word-line cutting structures extending through the gate electrode layers, the word-line cutting structures extend in each of the first direction and a second direction intersecting the first direction and parallel to the first face of the plate layer, wherein the word-line cutting structures are spaced apart from each other along a third direction intersecting each of the first and second directions and parallel to the first face of the plate layer, via structures disposed on the second face of the plate layer, the via structures extending in the third direction, wherein the via structures are spaced apart from each other along the second direction, each of the via structures includes a bottom face facing the second face of the plate layer and a top face opposite the bottom face; via connecting structures disposed on the top face of the via structures, the via connecting structures extending in the second direction, wherein the via connecting structures are spaced apart from each other along the third direction, each of the via connecting structures includes a bottom face facing the top face of the via structures and a top face opposite the bottom face; and second bonding metal layers disposed under the channel structures and the gate electrode layers and connected to the first bonding metal layers, wherein a width of the bottom face of each of the via structures is greater than a width of the top face of each of the via structures, wherein a width of the bottom face of each of the via connecting structures is less than a width of the top face of each of the via connecting structures.

2 . The semiconductor device of claim 1 , wherein the semiconductor device further comprises an insulating layer disposed on the second face of the plate layer and directly contacting a side face of each of the via structures.

3 . The semiconductor device of claim 1 , wherein each of the via structures does not contact a side face of the plate layer.

4 . The semiconductor device of claim 1 , wherein a length along the second direction of each of the via structures is different from a length along the second direction of each of the via connecting structures.

5 . The semiconductor device of claim 1 , wherein:
the plate layer includes polysilicon; each of the via structures includes tungsten (W), each of the via connecting structures includes aluminum (Al).

6 . The semiconductor device of claim 1 , wherein in a plan view of the semiconductor device, the second substrate structure includes a first area including the channel structures, and second and third areas sequentially arranged outwardly from the first area,
wherein the second substrate structure includes: cell contact structures disposed in the second area, each of the cell contact structures are electrically connected to one of the gate electrode layers; dummy channel structures disposed in the second area, the dummy channel structures are electrically isolated from the gate electrode layers; source contact structures disposed in the second area, the source contact structures do not extend through the gate electrode layers and extending through at least a portion of the plate layer; and through structures disposed in the third area, the through structures are not disposed on the plate layer, wherein the through structures are electrically connected to the circuit element.

7 . The semiconductor device of claim 6 , wherein each of the via structures includes:
a first extension disposed in the first and second areas and extending in the third direction; and a first spaced portion disposed in the third area and spaced apart from the first extension, wherein the first spaced portion is connected to one of the through structures.

8 . The semiconductor device of claim 7 , wherein the first extension includes a plurality of extensions spaced apart from each other in the third direction.

9 . The semiconductor device of claim 6 , wherein each of the via connecting structures includes:
a second extension disposed in the first and second areas and extending in the second direction, and a second spaced portion disposed in the third area and spaced apart from the second extension, wherein the second spaced portion is connected to one of the through structures.

10 . The semiconductor device of claim 9 , wherein the second extension includes a plurality of extensions, wherein the plurality of extensions and the word-line cutting structures are arranged alternately with each other in the third direction.

11 . The semiconductor device of claim 9 , wherein the second extension has a plate shape and is disposed on the word-line cutting structures.

12 . A semiconductor device comprising:
a first substrate structure including a first substrate, circuit elements disposed on the first substrate, and first bonding metal layers disposed on the circuit elements; and a second substrate structure disposed on the first substrate structure, wherein the second substrate structure is connected to the first substrate structure, wherein the second substrate structure includes: a plate layer including a conductive material; gate electrode layers disposed on a bottom face of the plate layer, the gate electrode layers are stacked on top of each other and spaced apart from each other along a vertical direction perpendicular to the bottom face of the plate layer; channel structures extending through the gate electrode layers in the vertical direction, wherein each of the channel structures includes a channel layer; word-line cutting structures extending through the gate electrode layers and extending in a first direction parallel to the bottom face of the plate layer; via structures disposed on the plate layer and extending in a second direction intersecting the first direction, wherein the via structures are spaced apart from each other along the first direction; via connecting structures disposed on a top surface of the via structures, the via connecting structures extending in the first direction, wherein the via connecting structures are spaced apart from each other along the second direction; and second bonding metal layers disposed under the channel structures and the gate electrode layers and connected to the first bonding metal layers, wherein in a plan view of the semiconductor device, the second substrate structure includes a first area including the channel structures, and a second area around the first area, wherein each of the via structures includes:
a first extension disposed in the first area and extending in the second direction; and
a first spaced portion disposed in the second area and spaced apart from the first extension in each of the first and second directions,
wherein each of the via connec

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ah Reum
• Yang Woo Sung
• Gu Ji Mo
• Kim Jao Ho
• Sung Suk Kang

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H01L23/5226 Primary

  Electricity · mapped topic