Method of manufacturing integrated circuit device

Patent metadata

Field	Value
Publication number	US-2024071771-A1
Application number	US-202318355520-A
Country	US
Kind code	A1
Filing date	Jul 20, 2023
Priority date	Aug 31, 2022
Publication date	Feb 29, 2024
Grant date	—

Abstract

A method of manufacturing an integrated circuit device includes preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.

First claim

What is claimed is:

1 . A method of manufacturing an integrated circuit device, the method comprising:
preparing a semiconductor substrate having an active area and a field area; sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate; removing a portion of the third sacrificial layer to form a first sacrificial pattern; removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern; removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern; removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern; and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench, wherein the first sacrificial layer comprises polysilicon.

2 . The method of claim 1 , wherein the forming of the second sacrificial pattern comprises:
forming a first mask layer conformally covering the first sacrificial pattern; partially removing the first mask layer to form a first mask pattern and to expose the first sacrificial pattern and the second sacrificial layer; and removing a portion of the second sacrificial layer and the first sacrificial pattern by using the first mask pattern as an etch mask.

3 . The method of claim 1 , wherein the forming of the third sacrificial pattern comprises:
forming a second mask layer conformally covering the second sacrificial pattern; partially removing the second mask layer to form a second mask pattern and to expose the second sacrificial pattern and the first sacrificial layer; and removing a portion of the first sacrificial layer and the second sacrificial pattern by using the second mask pattern as an etch mask.

4 . The method of claim 3 , wherein the removing of the portion of the first sacrificial layer comprises:
at least partially removing the second mask pattern through an etching process; and cleaning the semiconductor substrate by using hydrogen fluoride (HF).

5 . The method of claim 1 , wherein the forming of the buried pattern comprises:
forming a third mask layer conformally covering the third sacrificial pattern; partially removing the third mask layer to form a third mask pattern and to expose the third sacrificial pattern; and removing a portion of the buried layer and the third sacrificial pattern by using the third mask pattern as an etch mask.

6 . The method of claim 1 , wherein the forming of the word line trench comprises:
partially removing each of the lower insulation layer and the semiconductor substrate by using the buried pattern as an etch mask; and ashing the semiconductor substrate in an oxygen-containing atmosphere.

7 . The method of claim 1 , wherein each of the second sacrificial layer and the third sacrificial layer comprises a double layer with a first layer of the double layer having an etch selectivity with respect to a second layer of the double layer.

8 . The method of claim 7 , wherein the double layer of at least one of the second sacrificial layer and the third sacrificial layer comprises a spin-on hardmask film as the first layer and silicon oxynitride as the second layer, the silicon oxynitride covering the spin-on hardmask film.

9 . The method of claim 1 , wherein the buried layer comprises a single layer including an amorphous carbon layer.

10 . The method of claim 1 , wherein the word line trench passes through the active area and the field area.

11 . A method of manufacturing an integrated circuit device, the method comprising:
forming a semiconductor substrate having a peripheral circuit area and a cell array area; forming a lower insulation layer on the semiconductor substrate; forming a buried layer on the lower insulation layer; forming a first sacrificial layer on the buried layer, the first sacrificial layer including polysilicon; forming a second sacrificial layer, including a first lower sacrificial layer and a first upper sacrificial layer having an etch selectivity with respect to each other, on the first sacrificial layer; forming a third sacrificial layer, including a second lower sacrificial layer and a second upper sacrificial layer having an etch selectivity with respect to each other, on the second sacrificial layer; removing a portion of the third sacrificial layer to form a first sacrificial pattern; removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern; removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern; removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern; and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.

12 . The method of claim 11 , wherein the forming of the buried pattern comprises:
forming a mask layer conformally covering the third sacrificial pattern; partially removing the mask layer to form a mask pattern and expose the third sacrificial pattern; forming a word line mask exposing the cell array area; and removing a portion of the buried layer and the third sacrificial pattern by using the mask pattern as an etch mask to form the buried pattern.

13 . The method of claim 11 , wherein the forming of the buried pattern comprises:
forming a mask layer conformally covering the third sacrificial pattern; forming a word line mask exposing the cell array area; partially removing the mask layer to form a mask pattern and expose the third sacrificial pattern; and removing a portion of the buried layer and the third sacrificial pattern by using the mask pattern as an etch mask to form the buried pattern.

14 . The method of claim 11 , wherein the forming of the word line trench comprises, after the word line trench is formed in the semiconductor substrate by using the buried pattern as an etch mask, removing the buried pattern in an oxygen-containing atmosphere.

15 . The method of claim 11 , wherein
each of the first lower sacrificial layer and the second lower sacrificial layer comprises a spin-on hardmask, and each of the first upper sacrificial layer and the second upper sacrificial layer comprises silicon oxynitride.

16 . The method of claim 11 , wherein the buried layer comprises a single layer including an amorphous carbon layer.

17 . A method of manufacturing an integrated circuit device, the method comprising:
forming a semiconductor substrate having a peripheral circuit area and a cell array area including an active area and a field area; forming a lower insulation layer on the semiconductor substrate; forming a buried layer on the lower insulation layer; forming a first sacrificial layer on the buried layer, the first sacrificial layer including polysilicon; forming a second sacrificial layer, including a first lower sacrificial layer and a first upper sacrificial layer having an etch selectivity with respect to each other, on the first sacrificial layer; forming a third sacrificial layer, including a second lower sacrificial layer and a second upper sacrificial layer having an etch selectivity with respect to each other, on the second sacrificial layer; removing the third sacrificial layer to form a first sacri

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Youngwoo
• Park Yonghan
• Park Jiho
• Seong Geumjung
• Han Seunguk

Classifications

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/02 Primary

  for one transistor one-capacitor [1T-1C] memory cells · CPC title

• H01L21/31144 Primary

  Electricity · mapped topic