Intelligent management of ferroelectric memory in a data storage device

Patent metadata

Field	Value
Publication number	US-2024070070-A1
Application number	US-202318503118-A
Country	US
Kind code	A1
Filing date	Nov 6, 2023
Priority date	Apr 28, 2021
Publication date	Feb 29, 2024
Grant date	—

Abstract

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

First claim

What is claimed is:

1 . A method comprising:
responsive to execution of at least one read command from a client, retrieving speculative readback data from a main memory into a front-end cache arranged as a non-volatile memory (NVM) comprising ferroelectric memory element (FME) cells; and evaluating a write command from the client, providing a first status value to the client responsive to available cache lines in the front-end cache to accommodate writeback data associated with the write command, providing a second status value to the client responsive to a lack of available cache lines in the front-end cache to accommodate the writeback data associated with the write command.

2 . The method of claim 1 , further comprising writing the writeback data to the front-end cache responsive to the first status value, the retrieving of the speculative readback data and the writing of the writeback data carried out by an intelligent cache manager responsive to at least one input based on utilization of the front-end cache.

3 . The method of claim 2 , further comprising writing the writeback data to a second front-end cache not formed of FME cells responsive to the second status value.

4 . The method of claim 2 , further comprising receiving a mode select input from the client associated with utilization of the front-end cache as directed by the client.

5 . The method of claim 4 , wherein an amount of the speculative readback data retrieved from the main memory is selected responsive to the mode select input from the client.

6 . The method of claim 4 , wherein the first and second values are generated responsive to the mode select input from the client.

7 . The method of claim 2 , wherein the at least one input comprises at leas a selected one of a mode select input from the client, a cache hit rate observed upon the speculative readback data in the front-end cache, or a command history comprising recently issued and completed read/write commands from the client.

8 . The method of claim 2 , wherein the intelligent cache manager circuit implements a writeback caching strategy to manage the writing of the writeback data, including determining whether the writeback data are to be stored in the front-end cache or a different cache not formed of FME cells.

9 . The method of claim 8 , wherein the writeback caching strategy includes a determination of how long the writeback data stored in the front-end cache persists before being transferred to a main NVM data storage memory coupled to the front-end cache, the main NVM data storage memory comprising at least a selected one of flash memory or rotatable magnetic recording memory.

10 . The method of claim 2 , wherein the intelligent cache manager circuit implements a speculative readback strategy to manage the reading of the non-requested speculative readback data, including determining how long the speculative readback data are retained in the front-end cache.

11 . The method of claim 2 , wherein the intelligent cache manager implements an exception event processing strategy to manage the front-end cache responsive to an exception event associated with a loss of power to the front-end cache, including determining a priority regarding a transfer of the writeback data from the front-end cache to a main NVM data storage memory coupled to the front-end cache, the main NVM data storage memory comprising at least a selected one of flash memory or rotatable magnetic recording memory.

12 . The method of claim 2 , wherein the FME cells of the front-end cache are formed of at least a selected one of the following FME cell construction types: FeRAM cells, FeFET cells or FTJ cells.

13 . An apparatus comprising:
a main NVM memory store coupled to a front-end cache, the front-end cache arranged as a non-volatile memory (NVM) comprising ferroelectric memory element (FME) cells; and an intelligent cache manager circuit configured to generate a speculative readback data strategy in which non-requested speculative readback data are transferred to the front-end cache from the main NVM memory in anticipation of a future read command from a client, and a writeback data strategy to store writeback data provided by the client to the front end cache, the speculative writeback data strategy comprising providing a first status value to the client responsive to sufficient available capacity in the front-end cache to accommodate the writeback data.

14 . The apparatus of claim 13 , wherein the writeback data strategy further comprising providing a different second status value to the client responsive to insufficient available capacity in the front-end cache to accommodate the writeback data.

15 . The apparatus of claim 14 , further comprising a second front-end cache formed of non-FME based volatile or non-volatile memory cells, and wherein the intelligent cache manager circuit stores the writeback data to the second front-end cache responsive to the second status value.

16 . The apparatus of claim 14 , wherein the intelligent cache manager selects the respective speculative readback data strategy and the writeback data strategy responsive to a mode select input supplied by the client.

17 . The apparatus of claim 14 , wherein the writeback caching strategy includes a determination of how long the writeback data stored in the front-end cache persists before being jettisoned therefrom to another memory location.

18 . The apparatus of claim 14 , wherein the writeback caching strategy includes jettisoning at least a portion of the speculative readback data from the front-end cache to accommodate the writeback data in the front-end cache.

19 . The apparatus of claim 14 , wherein the intelligent cache manager circuit further generates an exception event processing strategy comprising a determination of priority regarding a transfer of the writeback data from the front-end cache to the main NVM data storage memory prior to a loss of available applied power to the front-end cache.

20 . The apparatus of claim 14 , wherein the FME cells of the front-end cache are managed by the intelligent cache manager to sustain a selected quality of service data transfer level.

Assignees

• Seagate Technology Llc

Inventors

• Trantham Jon D
• Viraraghavan Praveen
• Dykes John W
• Gilbert Ian J
• Kalarickal Sangita Shreedharan
• Totin Matthew J
• El-Batal Mohamad
• Mehta Darshana H

Classifications

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/60

  Details of cache memory · CPC title