Imaging element and imaging device

Patent metadata

Field	Value
Publication number	US-2024064433-A1
Application number	US-202118261364-A
Country	US
Kind code	A1
Filing date	Dec 28, 2021
Priority date	Jan 22, 2021
Publication date	Feb 22, 2024
Grant date	—

Abstract

The present technology relates to an imaging element and an imaging device that facilitate miniaturization of pixels.
The first substrate including a plurality of detection pixels that generates a voltage signal corresponding to a logarithmic value of a photocurrent, and the second substrate including a detection circuit that detects whether the change amount of the voltage signal of a detection pixel indicated by an inputted selection signal among the plurality of detection pixels exceeds a predetermined threshold or not are stacked, and an element constituting the detection circuit is disposed in each of a first region on a back surface side and a second region on a front surface side of the second substrate. The present technology can be applied to, for example, an imaging element that detects an address event for each pixel.

First claim

1 . An imaging element comprising:
a first substrate including a plurality of detection pixels that generates a voltage signal corresponding to a logarithmic value of a photocurrent; and a second substrate including a detection circuit that detects whether a change amount of the voltage signal of a detection pixel indicated by an inputted selection signal among the plurality of detection pixels exceeds a predetermined threshold or not, the first substrate and the second substrate being stacked, wherein an element constituting the detection circuit is disposed in each of a first region on a back surface side and a second region on a front surface side of the second substrate.

2 . The imaging element according to claim 1 , further comprising
a separation layer that electrically separates the first region and the second region from each other, the separation layer being provided between the first region and the second region.

3 . The imaging element according to claim 1 ,
wherein an element disposed in the first region and an element disposed in the second region have different S-value characteristics.

4 . The imaging element according to claim 1 ,
wherein an element disposed in the first region and an element disposed in the second region have different thermal resistances.

5 . The imaging element according to claim 1 ,
wherein an element disposed in the first region and an element disposed in the second region have different drive voltages.

6 . The imaging element according to claim 1 ,
wherein an element disposed in the first region and an element disposed in the second region have different gate interface orders.

7 . The imaging element according to claim 1 ,
wherein an element in the first substrate and an element in the second substrate are connected by a contact.

8 . The imaging element according to claim 1 ,
wherein a wiring provided in the first substrate and a wiring provided in the second substrate are bonded.

9 . The imaging element according to claim 1 ,
wherein a third substrate is further stacked on the second substrate.

10 . The imaging element according to claim 9 ,
wherein a wiring provided in the second substrate and a wiring provided in the third substrate are bonded.

11 . An imaging device comprising:
a plurality of detection pixels each configured to generate a voltage signal corresponding to a logarithmic value of a photocurrent; a detection circuit that detects whether a change amount of the voltage signal of a detection pixel indicated by an inputted selection signal among the plurality of detection pixels exceeds a predetermined threshold or not; and a signal processing unit that processes a detection signal indicating a detection result of the detection circuit, wherein an element constituting the detection circuit is disposed in each of a region on a back surface side and a region on a front surface side of a substrate including the detection circuit.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Miyake Shinichi
• Tomida Kazuyuki
• Niwa Atsumi

Classifications

• H10F39/809

  of hybrid image sensors · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/79 Primary

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title