Merged Power Delivery

US2024063715A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2024063715-A1
Application numberUS-202217820168-A
CountryUS
Kind codeA1
Filing dateAug 16, 2022
Priority dateAug 16, 2022
Publication dateFeb 22, 2024
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

First claim

Opening claim text (preview).

What is claimed is: 1 . An apparatus, comprising: a primary voltage regulator circuit configured to generate a primary supply voltage on a primary power supply node; an integrated circuit including a plurality of functional blocks coupled to a plurality of local supply nodes; and a plurality of bypass regulator circuits configured to source a plurality of bypass currents to the plurality of local supply nodes; and wherein the integrated circuit further include a plurality of local voltage regulator circuits including a particular local voltage regulated circuit configured to source, using the primary supply voltage, a supply current to a corresponding local power supply node of the plurality of local supply nodes in response to a determination that a voltage level of the corresponding local supply node is less than a threshold value. 2 . The apparatus of claim 1 , wherein the particular local voltage regulator circuit includes a device coupled between the primary power supply node and a particular local supply node of the plurality of local supply nodes, and wherein the device is configured to adjust a conductance between the primary power supply node and the particular local supply node based on a comparison of a voltage level of the particular local supply and a reference voltage. 3 . The apparatus of claim 1 , wherein the particular local voltage regulator circuit includes a capacitor, and wherein the particular local voltage regulator circuit is configured to: charge, during a first time period, the capacitor using the primary voltage level; and discharge, during a second time period subsequent to the first time period, the capacitor into a particular power supply node of the plurality of local supply nodes. 4 . The apparatus of claim 1 , wherein a particular bypass regulator circuit of the plurality of bypass regulator circuits includes a resistor coupled to a corresponding local supply node of the plurality of local supply nodes. 5 . The apparatus of claim 4 , wherein the particular bypass regulator circuit further includes a switching circuit configured to source, using a voltage level of an input power node, a corresponding bypass current of the plurality of bypass currents to the corresponding local supply node via the resistor. 6 . The apparatus of claim 5 , wherein the particular bypass regulator circuit further includes a control circuit configured to: measure a voltage drop across the resistor to determine a value of the corresponding bypass current; and adjust operation of the switching circuit based on the value of the corresponding bypass current. 7 . A method, comprising: generating, by a plurality of bypass regulator circuits, a plurality of local supply voltages on a plurality of local power supply nodes coupled to corresponding ones of a plurality of circuit blocks included in a first integrated circuit; generating, by a primary voltage regulator circuit, a primary supply voltage on a primary power supply node; and clamping, by a plurality of local voltage regulator circuits included on the first integrated circuit and using the primary supply voltage, respective voltage levels on the plurality of local power supply nodes. 8 . The method of claim 7 , wherein clamping the respective voltage levels on the plurality of local power supply nodes includes modifying a conductance between the primary power supply node and a particular local power supply node of the plurality of local power supply nodes based on a comparison of a voltage level of the particular local power supply node and a reference voltage. 9 . The method of claim 7 , wherein clamping the respective voltage levels of the plurality of local supply nodes includes: charging, by a particular local voltage regulator circuit of the plurality of local voltage regulator circuits, at least one capacitor using the primary supply voltage; and discharging, by the particular local voltage regulator circuit, the at least one capacitor into a particular local power supply node of the plurality of local power supply nodes coupled to the particular local voltage regulator circuit. 10 . The method of claim 7 , further comprising decoupling, in response to detecting a power gating operation, a particular local voltage regulator circuit of the plurality of local voltage regulator circuits and a corresponding one of the plurality of bypass regulator circuits from a corresponding one of the plurality of local supply nodes. 11 . The method of claim 7 , wherein the first integrated circuit, the primary regulator circuit, and the plurality of bypass regulator circuits are coupled to a common circuit board. 12 . The method of claim 7 , wherein the plurality of bypass regulator circuits are included in a second integrated circuit, and wherein the first integrated circuit, the second integrated circuit, and the primary voltage regulator circuit are coupled to a common circuit board. 13 . The method of claim 7 , wherein the primary voltage regulator circuit and the plurality of bypass regulator circuits are included in a second integrated circuit that is coupled to a common circuit board along with the first integrated circuit. 14 . An apparatus, comprising: a primary power converter circuit configured to generate a primary supply voltage on a primary power supply node; an auxiliary power converter circuit configured to generate an auxiliary supply voltage on an auxiliary power supply node; and an integrated circuit including: a first plurality of wiring networks coupled between the primary power supply node and a corresponding plurality of local power supply nodes; a second plurality of wiring networks coupled between the auxiliary power supply node and a corresponding plurality of local auxiliary nodes; a plurality of local voltage regulator circuits configured to source, using corresponding ones of the plurality of local auxiliary nodes, a plurality of currents to the plurality of local power supply nodes; a plurality of functional circuit blocks coupled to the plurality of local power supply nodes; and a selection circuit configured to select a particular one of the plurality of local power supply nodes to generate a feedback signal; and wherein the primary power converter circuit is further configured to adjust a value of the primary supply voltage using the feedback signal. 15 . The apparatus of claim 14 , wherein the plurality of local voltage regulator circuits includes a particular local voltage regulator circuit configured to adjust a conductance between a particular local auxiliary node of the plurality of local auxiliary nodes and a particular local power supply node of the plurality of local power supply nodes using a voltage level of the local power supply node. 16 . The apparatus of claim 15 , wherein the particular local voltage regulator circuit includes a plurality of devices coupled between the particular local auxiliary node and the particular local power supply node, and wherein to adjust the conductance between the particular local auxiliary node and the particular local power supply node, the particular local voltage regulator circuit is further configured to: perform a comparison of the voltage level of the local power supply node to a reference voltage; and activate one or more of the plurality of devices using a result of the comparison. 17 . The apparatus of claim 16 , wherein to perform the comparison, the particular local voltage regulator circuit is further configured to filter the voltage level of the local power supply node.

Assignees

Inventors

Classifications

  • H02M3/07Primary

    using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

  • Converter structures employing plural converter units, other than for parallel operation of the units on a single load · CPC title

  • H02M1/008Primary

    Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators · CPC title

  • with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation · CPC title

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What does patent US2024063715A1 cover?
A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multip…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification H02M3/07. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Feb 22 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).