Sacrificial passivation film deposition method, trench etching method and semiconductor processing apparatus using low-temperature ald process

Patent metadata

Field	Value
Publication number	US-2024063025-A1
Application number	US-202318213894-A
Country	US
Kind code	A1
Filing date	Jun 26, 2023
Priority date	Aug 11, 2022
Publication date	Feb 22, 2024
Grant date	—

Abstract

A sacrificial passivation film deposition method according to an exemplary embodiment of the present disclosure may include: depositing a primary sacrificial passivation film on an entire surface of a substrate using a thermal ALD (T-ALD) process; and additionally depositing a secondary sacrificial passivation film on an upper surface and at least a portion of a side surface of an upper portion of the primary sacrificial passivation film using a plasma-ALD (P-ALD) process.

First claim

What is claimed is:

1 . A sacrificial passivation film deposition method using a low-temperature atomic layer deposition (ALD) process, comprising:
depositing a primary sacrificial passivation film on an entire surface of a substrate using a thermal ALD (T-ALD) process; and additionally depositing a secondary sacrificial passivation film on an upper surface and at least a portion of a side surface of an upper portion of the primary sacrificial passivation film using a plasma-ALD (P-ALD) process.

2 . The sacrificial passivation film deposition method of claim 1 , wherein the depositing of the primary sacrificial passivation film and the depositing of secondary sacrificial passivation film are performed at a low-temperature of 150° C. or less.

3 . The sacrificial passivation film deposition method of claim 2 , wherein the low-temperature includes a temperature of 0° C. or less.

4 . The sacrificial passivation film deposition method of claim 1 , wherein a silicon precursor used for depositing the primary sacrificial passivation film in the T-ALD process and a silicon precursor used for depositing the secondary sacrificial passivation film in the P-ALD process are the same as each other.

5 . The sacrificial passivation film deposition method of claim 4 , wherein the silicon precursor is a silylamine compound represented by the following Formula 1:

wherein R 1 to R 6 are each independently (C 1 -C 5 ) alkyl or (C 2 -C 5 ) alkenyl, or R 1 and R 2 and R 5 and R 6 are independently connected to each other to form a ring.

6 . The sacrificial passivation film deposition method of claim 4 , wherein the silicon precursor is at least one of DIPAS, BDEAS, DSBAS, and BDIPADS.

7 . The sacrificial passivation film deposition method of claim 1 , wherein a silicon precursor used for depositing the primary sacrificial passivation film in the T-ALD process and a silicon precursor used for depositing the secondary sacrificial passivation film in the P-ALD process are different from each other.

8 . The sacrificial passivation film deposition method of claim 5 , wherein a carbon (C) content of the sacrificial passivation film manufactured by the silylamine compound is 0.96 to 20%.

9 . The sacrificial passivation film deposition method of claim 5 , wherein the primary sacrificial passivation film or the secondary sacrificial passivation film has a thickness of 1 to 20 Å.

10 . The sacrificial passivation film deposition method of claim 5 , wherein the primary sacrificial passivation film or the secondary sacrificial passivation film is deposited on the entire surface of the substrate by performing the T-ALD process or the P-ALD process in a plurality of cycles, and the number of the plurality of cycles is 1 to 20 cycles.

11 . A trench etching method using a low-temperature atomic layer deposition (ALD) process, comprising:
depositing a target layer on a substrate; etching a portion of the target layer; and completing etching of the target layer, wherein the etching of the portion of the target layer includes: depositing a primary sacrificial passivation film on an entire surface of the target layer using a thermal ALD (T-ALD) process; and additionally depositing a secondary sacrificial passivation film on an upper surface and a side surface of an upper portion of the primary sacrificial passivation film using a plasma-ALD (P-ALD) process.

12 . The trench etching method of claim 11 , wherein the primary sacrificial passivation film and the secondary sacrificial passivation film are deposited on the target layer of which the portion is etched.

13 . The trench etching method of claim 11 , wherein the target layer is a portion of a trench structure of a high aspect ratio formed by high aspect ratio etching, and the trench structure of the high aspect ratio includes at least a channel hole (CHH), a channel hole mask (CHM), and an amorphous carbon layer (ACL) in a 3D-NAND flash memory manufacturing process.

14 . The trench etching method of claim 11 , wherein the depositing of the primary sacrificial passivation film and the depositing of the secondary sacrificial passivation film is performed at a low-temperature of 150° C. or less.

15 . The trench etching method of claim 11 , wherein a silicon precursor used for depositing the primary sacrificial passivation film in the T-ALD process and a silicon precursor used for depositing the secondary sacrificial passivation film in the P-ALD process are the same as each other.

16 . The trench etching method of claim 15 , wherein the silicon precursor is a silylamine compound represented by the following Formula 1:

wherein R 1 to R 6 are each independently (C 1 -C 5 ) alkyl or (C 2 -C 5 ) alkenyl, or R 1 and R 2 and R 5 and R 6 are independently connected to each other to form a ring.

17 . The trench etching method of claim 11 , wherein when the deposited primary sacrificial passivation film or the secondary sacrificial passivation film deposited in the etching of the portion of the target layer is removed, a process of depositing and etching the primary sacrificial passivation film or the secondary sacrificial passivation film are repeatedly performed.

18 . The trench etching method of claim 11 , wherein in the completing of the etching of the target layer, the primary sacrificial passivation film and the secondary sacrificial passivation film are removed.

19 . A semiconductor processing apparatus that performs the trench etching method using the low-temperature atomic layer deposition (ALD) process of claim 11 , comprising:
a first chamber depositing the primary sacrificial passivation film on the target layer, and a second chamber depositing the secondary sacrificial passivation film on the primary sacrificial passivation film.

20 . The semiconductor processing apparatus of claim 19 , wherein the first chamber and the second chamber are the same chamber, and
the etching is performed on the target layer in the first chamber or the second chamber.

Assignees

• Semes Co Ltd

Inventors

• Hong Jin Hee
• Kim Yun Sang
• Jeon Min Sung
• Jeon Young Eun
• Choi Sung Min
• Jin Young Jo
• Jang Dong Young

Classifications

• H10P72/0421 Primary

  for drying etching · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title