Write duty cycle calibration on a memory device

Patent metadata

Field	Value
Publication number	US-2024046976-A1
Application number	US-202318225878-A
Country	US
Kind code	A1
Filing date	Jul 25, 2023
Priority date	Aug 4, 2022
Publication date	Feb 8, 2024
Grant date	—

Abstract

Operations include generating a voltage level associated with a digital signal corresponding to a write operation associated with one or more memory cells of a memory device, comparing the voltage level to a reference voltage level to generate a comparison result, generating based on the comparison result, a command to adjust a duty cycle associated with the digital signal; and adjusting the duty cycle associated with digital signal based on the command.

First claim

What is claimed is:

1 . A memory device comprising:
a first circuit to generate a voltage level associated with a digital signal corresponding to a write operation associated with one or more memory cells of the memory device; a second circuit to compare the voltage level to a reference voltage level to generate a comparison result; control logic operatively coupled to the second circuit, the control logic to generate, based on the comparison result, a command to adjust a duty cycle associated with the digital signal; and a third circuit operatively coupled to the control logic, the third circuit to:
receive the command from the control logic; and
adjust the duty cycle associated with digital signal based on the command.

2 . The memory device of claim 1 , wherein the control logic receives a calibration command from a memory sub-system controller associated with the memory device, wherein the calibration command identifies the digital signal.

3 . The memory device of claim 1 , wherein the first circuit comprises a low pass filter.

4 . The memory device of claim 1 , wherein the comparison result generated by the second circuit is one of:
the voltage level associated with the digital signal is greater than the reference voltage level; or the voltage level associated with the digital signal is less than the reference voltage level.

5 . The memory device of claim 1 , wherein the third circuit comprises a set of logic gates that are controlled based on the command.

6 . The memory device of claim 1 , wherein the third circuit generates an adjusted digital signal comprising an adjusted duty cycle.

7 . The memory device of claim 6 , wherein the first circuit generate an updated voltage level associated with the adjusted digital signal; wherein the second circuit compares the updated voltage level to the reference voltage level to generate an updated comparison result; and wherein the control logic generates, based on the updated comparison result, an updated command to adjust the adjusted duty cycle associated with the adjusted digital signal.

8 . The memory device of claim 1 , wherein the duty cycle is adjusted by the third circuit to a target duty cycle level.

9 . A memory device comprising:
an array of memory cells; and control logic, operatively coupled with the array of memory cells, to perform operations comprising:
receiving a comparison result based on a comparison of a reference voltage level and a voltage level associated with a digital signal corresponding to a write operation associated with at least a portion of the array of memory cells; and
generating based on the comparison result, a command to adjust a duty cycle associated with the digital signal.

10 . The memory device of claim 9 , wherein the control logic provides the command to a circuit configured to adjust the duty cycle of the digital signal in accordance with the command.

11 . The memory device of claim 9 , further comprising a low pass filter to determine the voltage level associated with the digital signal.

12 . The memory device of claim 11 , further comprising a comparator circuit to generate the comparison result based on comparing the reference voltage level and the voltage level associated with the digital signal.

13 . The memory device of claim 9 , further comprising a circuit configured to adjust the duty cycle of the digital signal based on the command received from the control logic.

14 . A method comprising:
generating a voltage level associated with a digital signal corresponding to a write operation associated with one or more memory cells of a memory device; comparing the voltage level to a reference voltage level to generate a comparison result; generating, by a processing device, based on the comparison result, a command to adjust a duty cycle associated with the digital signal; and adjusting the duty cycle associated with digital signal based on the command.

15 . The method of claim 14 , further comprising receiving a calibration command from a memory sub-system controller associated with the memory device, wherein the calibration command identifies the digital signal.

16 . The method of claim 14 , wherein the comparison result is one of:
the voltage level associated with the digital signal is greater than the reference voltage level; or the voltage level associated with the digital signal is less than the reference voltage level.

17 . The method of claim 14 , wherein the duty cycle is adjusted by controlling a set of logic gates based on the command.

18 . The method of claim 14 , further comprising generating an adjusted digital signal comprising an adjusted duty cycle.

19 . The method of claim 18 , further comprising:
generating an updated voltage level associated with the adjusted digital signal; comparing the updated voltage level to the reference voltage level to generate an updated comparison result; and generating, based on the updated comparison result, an updated command to adjust the adjusted duty cycle associated with the adjusted digital signal.

20 . The method of claim 14 , wherein the duty cycle is adjusted to a target duty cycle level.

Assignees

• Micron Technology Inc

Inventors

• Pilolli Luigi
• Wang Guan
• D’Esposito Rosario
• Proescholdt Andrew
• Botticchio Lucia
• Di Loreto Luca

Classifications

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4099

  Dummy cell treatment; Reference voltage generators · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title