Gallium nitride device and method for manufacturing high electron mobility transistor

Patent metadata

Field	Value
Publication number	US-2024038847-A1
Application number	US-202217892098-A
Country	US
Kind code	A1
Filing date	Aug 21, 2022
Priority date	Jul 29, 2022
Publication date	Feb 1, 2024
Grant date	—

Abstract

A gallium nitride device and a method for manufacturing a high electron mobility transistor are provided. The gallium nitride device includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a cap layer disposed on the barrier layer, a gate disposed on the cap layer, a source, a drain, and ohmic sidewall dams. The source and the drain are formed in the cap layer and the barrier layer. Each of the source and the drain has a trench portion, and a contact below the trench portion and protruding into the channel layer. The ohmic sidewall dams are disposed on a sidewall of the trench portion of each of the source and the drain.

First claim

What is claimed is:

1 . A gallium nitride device, comprising:
a substrate; a channel layer, disposed on the substrate; a barrier layer, disposed on the channel layer; a cap layer, disposed on the barrier layer; a gate, formed on the cap layer; a source and a drain, formed in the cap layer and the barrier layer, wherein each of the source and the drain has a trench portion, and a contact below the trench portion and protruding into the channel layer; and a plurality of ohmic sidewall dams, disposed on a sidewall of the trench portion of each of the source and the drain.

2 . The gallium nitride device according to claim 1 , wherein
a two-dimensional electron gas is generated in the channel layer close to the barrier layer, and the contact of each of the source and the drain is in direct contact with the two-dimensional electron gas.

3 . The gallium nitride device according to claim 1 , wherein
a material of the source and the drain comprises Au, Mo, Al, Ti, or a combination thereof.

4 . The gallium nitride device according to claim 1 , further comprising:
a passivation layer, covering the gate and the cap layer.

5 . The gallium nitride device according to claim 4 , wherein
the plurality of ohmic sidewall dams are further disposed between the gate and the passivation layer.

6 . The gallium nitride device according to claim 1 , wherein
a material of the plurality of ohmic sidewall dams comprises silicon nitride, silicon oxide, aluminum oxide, or a combination thereof.

7 . The gallium nitride device according to claim 1 , wherein
each of the source and the drain has a multi-layered structure composed of a plurality of bowl-shaped stacks.

8 . A gallium nitride device, comprising:
a substrate; a channel layer, disposed on the substrate; a barrier layer, disposed on the channel layer; a cap layer, disposed on the barrier layer; a gate, formed on the cap layer; a source and a drain, formed in the cap layer and the barrier layer, wherein a material of the source and the drain comprises Au and Ti; a plurality of ohmic sidewall dams, disposed on a sidewall of the source and the drain; a plurality of TiN protrusions, located below the source and the drain and protruding into the channel layer; and an Au-containing layer, located below the plurality of TiN protrusions.

9 . The gallium nitride device according to claim 8 , wherein
a two-dimensional electron gas is generated in the channel layer close to the barrier layer, and the plurality of TiN protrusions are in direct contact with the two-dimensional electron gas.

10 . The gallium nitride device according to claim 8 , wherein
the material of the source and the drain further comprises Mo, Al, or a combination thereof.

11 . The gallium nitride device according to claim 8 , further comprising:
a passivation layer, covering the gate and the cap layer.

12 . The gallium nitride device according to claim 11 , wherein
the plurality of ohmic sidewall dams are further disposed between the gate and the passivation layer.

13 . The gallium nitride device according to claim 8 , wherein
a material of the plurality of ohmic sidewall dams comprises silicon nitride, silicon oxide, aluminum oxide, or a combination thereof.

14 . The gallium nitride device according to claim 8 , wherein
each of the source and the drain has a multi-layered structure composed of a plurality of bowl-shaped stacks.

15 . A method for manufacturing a high electron mobility transistor, comprising:
forming a channel layer on a substrate; forming a barrier layer on the channel layer; forming a cap layer on the barrier layer; forming a gate on the cap layer; forming a plurality of trenches penetrating through the cap layer and the barrier layer; forming a plurality of ohmic sidewall dams on a sidewall of the plurality of trenches; forming a plurality of openings below the plurality of trenches into the channel layer; and forming a source and a drain in the plurality of trenches and the plurality of openings, wherein the source and the drain are separated from the cap layer by the plurality of ohmic sidewall dams.

16 . The method for manufacturing a high electron mobility transistor according to claim 15 , wherein
a method for forming the source and the drain comprises a dual damascene process.

17 . The method for manufacturing a high electron mobility transistor according to claim 15 , wherein forming the source and the drain comprises:
depositing a metal material in the plurality of trenches and the plurality of openings; and patterning the metal material.

18 . The method for manufacturing a high electron mobility transistor according to claim 15 , wherein forming the source and the drain comprises:
depositing a metal material to fill the plurality of trenches and the plurality of openings; and lifting off the metal material except that in the plurality of trenches and the plurality of openings.

19 . The method for manufacturing a high electron mobility transistor according to claim 15 , wherein forming the plurality of ohmic sidewall dams comprises:
conformally depositing a dielectric material on the sidewall and a bottom of each of the plurality of trenches; and removing a portion of the dielectric material at the bottom of each of the plurality of trenches.

20 . The method for manufacturing a high electron mobility transistor according to claim 19 , wherein a method for depositing the dielectric material comprises an atomic layer deposition method.

Assignees

• United Microelectronics Corp

Inventors

• Yeh Chih Tung
• Hou Chun-Liang

Classifications

• H10D64/0125

  characterised by the sectional shape, e.g. T or inverted T · CPC title

• H10D64/256 Primary

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503 Primary

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/475 Primary

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title