Low-dropout voltage regulator circuit and corresponding method of operation

Patent metadata

Field	Value
Publication number	US-2024036595-A1
Application number	US-202318224897-A
Country	US
Kind code	A1
Filing date	Jul 21, 2023
Priority date	Jul 29, 2022
Publication date	Feb 1, 2024
Grant date	—

Abstract

A low-drop out voltage regulator includes a pass element arranged between an input terminal and an output terminal, a feedback network configured to produce a feedback voltage derived from an output voltage, and an error amplifier configured to drive the pass element as a function of a difference between the feedback voltage and a reference voltage. An output transistor coupled in series with the pass element is controlled by a mode selection circuit. In response to assertion of a mode selection signal, the mode selection circuit turns on the output transistor to sink a current with a controlled magnitude from the output node. In response to de-assertion of the mode selection signal, the mode selection circuit sinks a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.

First claim

1 . A circuit, comprising:
a voltage regulator circuit configured to generate a regulated voltage at an output node; a transistor coupled between the output node and a reference node; and a mode selection circuit coupled to a control terminal of the transistor and configured to: control the transistor to sink a current with a controlled magnitude from said output node to the reference node in response to a first logic state of a mode control signal, and sink a current with a controlled magnitude from the control terminal of the transistor in response to a second logic state of the mode control signal in order to turn off said transistor at a controlled rate.

2 . The circuit of claim 1 , wherein said mode selection circuit comprises:
a first current conduction path including a first current source configured to source a first current, said first current conduction path enabled in response to the first logic state of the mode control signal; wherein said first current conduction path is coupled in a first current mirroring relationship with the transistor circuit.

3 . The circuit of claim 2 , wherein said mode selection circuit further comprises:
a second current conduction path including a second current source configured to source a second current, said second current conduction path enabled in response to the second logic state of the mode control signal; wherein said second current conduction path is coupled in a second current mirroring relationship with a sinking transistor; and wherein said sinking transistor is coupled to the control terminal of the transistor.

4 . The circuit of claim 2 , wherein the first current mirroring relationship includes a plurality of coupling transistor connected in series with the control terminal of the transistor, said coupling transistors having control terminals configured to be switched to a conductive state in response to the first logic state of the mode control signal.

5 . The circuit of claim 2 , further comprising a control circuit configured to generate said mode selection signal.

6 . The circuit of claim 5 , wherein said control circuit asserts the mode control signal in the first logic state in response to a transition of the voltage regulator circuit from a low-power mode to a high-power mode with respect to a load coupled to the output node.

7 . The circuit of claim 6 , wherein said control circuit deasserts the mode selection signal in the second logic state in response to a transition of the voltage regulator circuit from the high-power mode to the low-power mode with respect to the load coupled to the output node.

8 . A method, comprising:
producing a regulated output voltage at an output node; and selectively controlling a transistor coupled between the output node and a reference node; wherein selectively controlling comprises:
controlling the transistor to sink a current with a controlled magnitude from said output node to the reference node in response to a first logic state of a mode control signal; and
sinking a current with a controlled magnitude from a control terminal of the transistor in response to a second logic state of the mode control signal in order to turn off said transistor at a controlled rate.

9 . A circuit, comprising:
a first input terminal and a second input terminal configured to receive an input voltage therebetween; a first output terminal and a second output terminal configured to produce a regulated output voltage therebetween, wherein the second input terminal and the second output terminal are coupled to a ground node; a feedback network configured to produce a feedback voltage indicative of the regulated output voltage; an error amplifier configured to produce a drive signal as a function of a difference between said feedback voltage and a reference voltage; a pass element arranged between said first input terminal and said first output terminal, wherein a conductivity of said pass element is modulated as a function of said drive signal; an output transistor arranged between said first output node and said ground node; and a mode selection circuit configured to receive a mode selection signal and control said output transistor as a function thereof, wherein:
in response to assertion of said mode selection signal, said mode selection circuit controls turning on said output transistor to sink a current with a controlled magnitude from said first output node; and
in response to de-assertion of said mode selection signal, said mode selection circuit sinks a current with a controlled magnitude from a control terminal of said output transistor to turn off said output transistor at a controlled rate.

10 . The circuit of claim 9 , wherein said mode selection circuit comprises a first current conduction path including a first current source configured to source a first current, an enabling transistor, and a diode-connected transistor arranged in series between a power supply node and said ground node,
wherein said enabling transistor is switched to a conductive state in response to assertion of said mode selection signal and switched to a non-conductive state in response to de-assertion of said mode selection signal, and wherein said diode-connected transistor and said output transistor are coupled to form a current mirror.

11 . The circuit of claim 10 , wherein said mode selection circuit comprises one or more coupling transistors with current conduction paths arranged in series between a control terminal of said diode-connected transistor and a control terminal of said output transistor, wherein said one or more coupling transistors are switched to a conductive state in response to assertion of said mode selection signal and switched to a non-conductive state in response to de-assertion of said mode selection signal.

12 . The circuit of claim 10 , wherein said mode selection circuit further comprises a capacitor coupled between a control terminal of said enabling transistor and said ground node.

13 . The circuit of claim 10 , wherein said mode selection circuit further comprises a gate-controlling transistor having a current conduction path arranged between a control terminal of said diode-connected transistor and said ground node, wherein said gate-controlling transistor is controlled in response to a complement of said mode selection signal, wherein the gate-controlling transistor is switched to a conductive state in response to de-assertion of said mode selection signal and switched to a non-conductive state in response to assertion of said mode selection signal.

14 . The circuit of claim 9 , wherein said mode selection circuit comprises a current mirror arrangement configured to selectively sink a second current from said control terminal of said output transistor in response to de-assertion of said mode selection signal.

15 . The circuit of claim 14 , wherein said mode selection circuit comprises a further enabling transistor having a current conduction path arranged between said current mirror arrangement and said control terminal of said output transistor, wherein said further enabling transistor is configured to receive a complement of said mode selection signal, wherein the further enabling transistor is switched to a conductive state in response to de-assertion of said mode selection signal and switched to a non-conductive state in response to assertion of said mode selection signal.

16 . The circuit of claim 14 , wherein said mode selection circuit comprises a further gate-controlling transistor having a current conduction path arranged between a control terminal of sai

Assignees

• St Microelectronics Srl

Inventors

• Ferlito Umberto
• Vaiana Michele
• Bruno Giuseppe
• Grasso Alfio Dario

Classifications

• G05F3/262

  using field-effect transistors only · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title