Semiconductor memory device and manufacturing method of semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2024032292-A1
Application number	US-202218081161-A
Country	US
Kind code	A1
Filing date	Dec 14, 2022
Priority date	Jul 20, 2022
Publication date	Jan 25, 2024
Grant date	—

Abstract

A semiconductor memory device includes: a substrate; a source stack structure and a source insulating layer disposed over the substrate to be spaced apart from each other; an isolation insulating layer disposed between the source stack structure and the source insulating layer; a first stack structure disposed over the source stack structure; a second stack structure disposed over the source insulating layer; a vertical structure penetrating the first stack structure and a portion of the source stack structure; and a lower contact penetrating the source insulating layer.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a substrate; a source stack structure and a source insulating layer disposed over the substrate to be spaced apart from each other; an isolation insulating layer disposed between the source stack structure and the source insulating layer; a first stack structure disposed over the source stack structure; a second stack structure disposed over the source insulating layer; a vertical structure penetrating the first stack structure and a portion of the source stack structure; and a lower contact penetrating the source insulating layer.

2 . The semiconductor memory device of claim 1 , wherein the source stack structure and the source insulating layer are disposed at the same level.

3 . The semiconductor memory device of claim 1 , wherein the isolation insulating layer includes a material that is different from that of the source insulating layer.

4 . The semiconductor memory device of claim 3 , wherein the isolation insulating layer includes a nitride layer.

5 . The semiconductor memory device of claim 1 , further comprising a peripheral circuit structure disposed between the substrate and the source stack structure and between the substrate and the source insulating layer,
wherein the lower contact is connected to the peripheral circuit structure.

6 . The semiconductor memory device of claim 5 , wherein the isolation insulating layer includes:
a first part disposed between the source stack structure and the source insulating layer; and a second part disposed between the source insulating layer and the peripheral circuit structure.

7 . The semiconductor memory device of claim 6 , wherein the second part of the isolation insulating layer is penetrated by the lower contact.

8 . The semiconductor memory device of claim 1 , further comprising an upper contact that penetrates the second stack structure and connects to the lower contact.

9 . The semiconductor memory device of claim 1 , wherein the lower contact is spaced apart from the source stack structure.

10 . The semiconductor memory device of claim 1 , wherein the isolation insulating layer is penetrated by the source insulating layer.

11 . The semiconductor memory device of claim 1 , wherein the source stack structure includes a first source layer and a second source layer, and
wherein the vertical structure penetrates the first source layer and a portion of the second source layer.

12 . The semiconductor memory device of claim 11 , wherein the source stack structure further includes a channel connection layer between the first source layer and the second source layer,
wherein the vertical structure includes a channel layer and a memory layer, and wherein the channel connection layer is connected to a portion of the channel layer, which is disposed at the same level as the channel connection layer.

13 . A semiconductor memory device comprising:
a source stack structure and a source insulating layer disposed over a peripheral circuit to be spaced apart from each other; an isolation insulating layer disposed between the source insulating layer and the source stack structure; a first stack structure including a plurality of interlayer insulating layers and a plurality of conductive layers over the source stack structure; a slit partitioning the first stack structure, the slit extending into the source stack structure; and a lower contact penetrating the source insulating layer.

14 . The semiconductor memory device of claim 13 , wherein the isolation insulating layer extends between the peripheral circuit structure and the source insulating layer.

15 . The semiconductor memory device of claim 13 , wherein the isolation insulating layer is disposed on a sidewall of the source stack structure.

16 . The semiconductor memory device of claim 13 , further comprising a second stack structure including a plurality of dummy interlayer insulating layers and a plurality of sacrificial layers, disposed over the source insulating layer.

17 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a peripheral circuit structure on a substrate that includes a first region and a second region; forming a preliminary source stack structure over the peripheral circuit structure; forming an opening that penetrates the preliminary source stack structure, the opening overlapping with the second region of the substrate; forming a first insulating material along a sidewall of the opening; forming a second insulating material inside the opening; forming a lower contact that penetrates the second insulating material; forming a preliminary stack structure in which first material layers and second material layers are alternately stacked over the preliminary source stack structure; forming a vertical structure penetrating the preliminary stack structure and a portion of the preliminary source stack structure, the vertical structure overlapping with the first region of the substrate; and forming an upper contact that penetrates the preliminary stack structure and connects to the lower contact, the upper contact overlapping with the second region of the substrate.

18 . The method of claim 17 , wherein the first insulating material includes:
a first part formed on a sidewall of the preliminary source stack structure; a second part formed on a bottom surface of the opening; and a third part formed to cover the preliminary source stack structure.

19 . The method of claim 18 , further comprising removing the second part and the third part of the first insulating material,
wherein the second insulating material is formed on the first part of the first insulating material.

20 . The method of claim 18 , further comprising planarizing the first insulating material and the second insulating material such that the third part of the first insulating material is removed.

21 . The method of claim 20 , wherein the lower contact penetrates the second part of the first insulating material.

22 . The method of claim 17 , further comprising:
forming a slit that penetrates the preliminary stack structure to overlap with the first region; and forming a gate stack structure by replacing the second material layers with third material layers through the slit, wherein the first material layers and the second material layers remain to overlap with the second region.

23 . The method of claim 22 , wherein the preliminary source stack structure includes a first source layer and a source sacrificial layer, which are stacked over the substrate,
wherein the vertical structure includes a channel layer and a memory layer, and wherein the method further comprises replacing a portion of the memory layer, which is surrounded by the source sacrificial layer, and the source sacrificial layer, with a channel connection layer.

24 . The method of claim 23 , wherein the first insulating material has a high etch selectivity with respect to the source sacrificial layer when compared to an etch selectivity of the second insulating material with respect to the source sacrificial layer.

25 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a preliminary source stack structure over a peripheral circuit structure, the preliminary source stack structure including a first source layer and a source sacrificial layer;

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title